Inventor profile of:

Jagadeesh Sankaran

City:

Allen, Texas

Country:

United States

Published Applications:

32

Last publication date:

2023-02-16

Top Assignees for applications by Jagadeesh Sankaran

The entities that hold a legal rights for patent applications filed by inventor Sankaran Jagadeesh:

Recent patent applications by Sankaran Jagadeesh

Jagadeesh Sankaran from Allen, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2023-02-16
US20230049454A1
Physics

PROCESSOR WITH TABLE LOOKUP UNIT

#2 | 2021-01-07
US20210004349A1
Physics

Vector table load instruction with address generation field to access table offset value

#3 | 2014-12-04
US20140355893A1
Physics

Vector processor calculation of local binary patterns

#4 | 2013-07-18
US20130185544A1
Physics

Processor with instruction variable data distribution

#5 | 2013-07-18
US20130185540A1
Physics

PROCESSOR WITH MULTI-LEVEL LOOPING VECTOR COPROCESSOR

#6 | 2013-07-18
US20130185539A1
Physics

Processor with table lookup processing unit

#7 | 2013-07-18
US20130185538A1
Physics

PROCESSOR WITH INTER-PROCESSING PATH COMMUNICATION

#8 | 2012-05-10
US20120117360A1
Physics

DEDICATED INSTRUCTIONS FOR VARIABLE LENGTH CODE INSERTION BY A DIGITAL SIGNAL PROCESSOR (DSP)

#9 | 2012-03-15
US20120066415A1
Physics

Methods and systems for direct memory access (DMA) in-flight status

#10 | 2012-01-19
US20120017067A1
Physics

On-demand predicate registers

#11 | 2011-12-29
US20110317762A1
Electricity

VIDEO ENCODER AND PACKETIZER WITH IMPROVED BANDWIDTH UTILIZATION

#12 | 2011-12-22
US20110310966A1
Electricity

SYNTAX ELEMENT DECODING

#13 | 2011-11-17
US20110280314A1
Physics

SLICE ENCODING AND DECODING PROCESSORS, CIRCUITS, DEVICES, SYSTEMS AND PROCESSES

#14 | 2009-01-01
US20090006665A1
Electricity

Modified Memory Architecture for CODECS With Multiple CPUs

#15 | 2009-01-01
US20090006664A1
Physics

Linked DMA Transfers in Video CODECS

#16 | 2009-01-01
US20090006037A1
Electricity

Accurate Benchmarking of CODECS With Multiple CPUs

#17 | 2008-10-30
US20080267513A1
Electricity

Method of CABAC significance MAP decoding suitable for use on VLIW data processors

#18 | 2008-10-30
US20080266151A1
Electricity

Method of CABAC coefficient magnitude and sign decoding suitable for use on VLIW data processors

#19 | 2008-06-24
US11202887
-

Cache friendly method for performing inverse discrete wavelet transform

#20 | 2007-02-13
US11235586
-

Video coding with CABAC

#21 | 2006-11-16
US20060259700A1
Physics

Providing information associated with a cache

#22 | 2006-11-16
US20060259698A1
Physics

Displaying cache information using mark-up techniques

#23 | 2006-11-16
US20060259696A1
Physics

DETERMINING DIFFERENCES BETWEEN CACHED COPIES OF AN ADDRESS

#24 | 2006-11-16
US20060259694A1
Physics

Cache inspection with inspection bypass feature

#25 | 2006-08-03
US20060174237A1
Physics

Mechanism for pipelining loops with irregular loop control

#26 | 2006-08-03
US20060174059A1
Physics

Speculative data loading using circular addressing or simulated circular addressing

#27 | 2005-09-15
US20050203928A1
Electricity

Register move instruction for section select of source operand

#28 | 2005-09-08
US20050198054A1
Physics

Speculative load of look up table entries based upon coarse index calculation in parallel with fine index calculation

#29 | 2005-06-02
US20050117653A1
Electricity

Loop deblock filtering of block coded video in a very long instruction word processor

#30 | 2005-03-17
US20050058358A1
Electricity

Method for planar processing of wavelet zero-tree data

#31 | 2005-01-06
US20050001746A1
Electricity

Method of context based adaptive binary arithmetic decoding with two part symbol decoding

#32 | 2005-01-06
US20050001745A1
Electricity

Method of context based adaptive binary arithmetic encoding with decoupled range re-normalization and bit insertion

InventorID:

347975 ⎘