Inventor profile of:

Yu-Lan Lo

City:

Hsinchu County

Country:

Taiwan

Published Applications:

15

Last publication date:

2021-01-14

Top Assignees for applications by Yu-Lan Lo

The entities that hold a legal rights for patent applications filed by inventor Lo Yu-Lan:

Recent patent applications by Lo Yu-Lan

Yu-Lan Lo from Hsinchu County, TW has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2021-01-14
US20210012050A1
Physics

Method of detecting relations between pins of circuit and computer program product thereof

#2 | 2020-11-12
US20200356716A1
Physics

IC design data base generating method, IC design method, and electronic device using the methods

#3 | 2020-10-08
US20200320241A1
Physics

Method of detecting a circuit malfunction and related device

#4 | 2020-09-10
US20200285791A1
Physics

CIRCUIT DESIGN METHOD AND ASSOCIATED COMPUTER PROGRAM PRODUCT

#5 | 2020-05-14
US20200151295A1
Physics

Method for determining IC voltage and method for finding relation between voltages and circuit parameters

#6 | 2019-12-19
US20190384868A1
Physics

METHOD AND APPARATUS FOR ADAPTIVE VOLTAGE SCALING TO ELIMINATE DELAY VARIATION OF WHOLE DESIGN

#7 | 2018-10-25
US20180307782A1
Physics

Circuit encoding method and circuit structure recognition method

#8 | 2017-12-21
US20170364619A1
Physics

Simulation method for mixed-signal circuit system and related electronic device

#9 | 2016-06-30
US20160188782A1
Physics

Computer program product for timing analysis of integrated circuit

#10 | 2015-03-05
US20150067623A1
Physics

TIMING ANALYSIS METHOD FOR NON-STANDARD CELL CIRCUIT AND ASSOCIATED MACHINE READABLE MEDIUM

#11 | 2014-08-07
US20140223398A1
Physics

Method for determining interface timing of integrated circuit automatically and related machine readable medium thereof

#12 | 2014-05-13
US14051459
-

Deadlock detection method and related machine readable medium

#13 | 2013-11-07
US20130298095A1
Physics

METHOD FOR CHECKING I/O CELL CONNECTIONS AND ASSOCIATED COMPUTER READABLE MEDIUM

#14 | 2013-07-18
US20130185683A1
Physics

Method of generating integrated circuit model

#15 | 2010-01-07
US20100005432A1
Physics

Method to inspect floating connection and floating net of integrated circuit

InventorID:

348183 ⎘