Boise, Idaho
United States
39
2024-08-29
The entities that hold a legal rights for patent applications filed by inventor Greeff Roy E.:
Roy E. Greeff from Boise, US has applied for patents for these inventions. The list has both pending applications and granted patents:
APPARATUSES AND METHODS FOR COUPLING A PLURALITY OF SEMICONDUCTOR DEVICES
#2 | 2024-06-06APPARATUSES AND METHODS FOR ENCODING AND DECODING OF SIGNAL LINES FOR MULTI-LEVEL COMMUNICATION ARCHITECTURES
#3 | 2024-04-04Memory device interface and method
#4 | 2024-02-29Memory device interface and method
#5 | 2024-02-22APPARATUSES AND METHODS FOR COUPLING A PLURALITY OF SEMICONDUCTOR DEVICES
#6 | 2024-02-08Multiple register clock driver loaded memory subsystem
#7 | 2023-04-06Apparatuses and methods for coupling a plurality of semiconductor devices
#8 | 2023-01-19Memory subsystem register clock driver clock teeing
#9 | 2022-10-27Memory device interface and method
#10 | 2022-10-20Channel modulation for a memory device
#11 | 2022-01-06Memory subsystem register clock driver clock teeing
#12 | 2022-01-06Apparatuses and methods for pulse response smearing of transmitted signals
#13 | 2022-01-06Configuring multiple register clock drivers of a memory subsystem
#14 | 2022-01-06Multiple register clock driver loaded memory subsystem
#15 | 2021-12-16Apparatuses and methods for coupling a plurality of semiconductor devices
#16 | 2021-10-14MEMORY DEVICE INTERFACE AND METHOD
#17 | 2021-09-09Apparatuses and methods for coupling a plurality of semiconductor devices
#18 | 2021-08-05Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures
#19 | 2020-08-27MEMORY DEVICE INTERFACE AND METHOD
#20 | 2020-08-27Memory device interface and method
#21 | 2020-07-23Channel modulation for a memory device
#22 | 2019-10-31Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures
#23 | 2019-02-28Clock tree structure in a memory system
#24 | 2019-01-10Apparatuses and methods for partial bit de-emphasis
#25 | 2018-09-20Apparatuses and methods for partial bit de-emphasis
#26 | 2018-04-17Apparatuses and methods for partial bit de-emphasis
#27 | 2017-07-27Apparatuses and methods for encoding and decoding of signal lines for multi-level communication architectures
#28 | 2015-04-09On-die termination apparatuses and methods
#29 | 2013-07-25Enhanced performance memory systems and methods
#30 | 2011-10-13Enhanced performance memory systems and methods
#31 | 2009-10-01Memory module and method having improved signal routing topology
#32 | 2009-03-05Enhanced performance memory systems and methods
#33 | 2008-02-14Memory module and method having improved signal routing topology
#34 | 2007-07-17Memory module and method having improved signal routing topology
#35 | 2006-09-14Method and system for generating reference voltages for signal receivers
#36 | 2006-03-02Method and system for generating reference voltages for signal receivers
#37 | 2006-02-02Memory module and method having improved signal routing topology
#38 | 2005-07-28Generation of memory test patterns for DLL calibration
#39 | 2005-02-10Memory module and method having improved signal routing topology
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