Kenneth J. Eldredge

Memory devices for pattern matching based on majority of cell pair match

Memory devices for pattern matching

Memory devices for comparing input data to data stored in memory cells coupled to a data line

Memory configured to perform logic operations on values representative of sensed characteristics of data lines and a threshold data value

Methods and apparatus for pattern matching in a memory containing sets of memory elements

Memory configured to generate a data value from a data line connected to more than one string of series-connected memory cells

Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line

Memory as a programmable logic device

Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line

Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line

Configurable operating mode memory device and methods of operation

Methods and apparatus for pattern matching having memory cell pairs coupled in series and coupled in parallel

Methods of operating memory

Memory as a programmable logic device

Configurable operating mode memory device and methods of operation

Memory device having a controller to enable and disable mode control circuitry of the controller

Methods and apparatus for pattern matching using redundant memory elements

Methods for pattern matching using multiple cell pairs

Memory as a programmable logic device

Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line

Methods of operating memory

Apparatus and methods of operating memory for exact and inexact searching of feature vectors

Neural network in a memory device

Memory as a programmable logic device

Using do not care data with feature vectors

Searching using multilevel cells and programming multilevel cells for searching

Memory as a programmable logic device

Memory devices configured to apply different weights to different strings of memory cells coupled to a data line and methods

Memory devices configured to apply different weights to different strings of memory cells coupled to a data line and methods

Compensation for solid state storage

Apparatuses and methods for reading and/or programming data in memory arrays having varying available storage ranges

Solid state storage element and method

Interpreting the data value stored by memory cell using a performance characteristic value

Assisted memory system

Memory configuration and method for calibrating read/write data based on performance characteristics of the memory configuration

Integrated circuit memory devices with MRAM voltage divider strings therein

Method of providing multiple logical bits per memory cell

Storage device having a probe to form structures for representing data states

Connection arrangements for electrical devices having a ledge on which contact terminals are provided

Systems and methods for translating voltage levels of digital signals

Increased magnetic memory array sizes and operating margins

System having a storage controller that modifies operation of a storage system based on the status of a data transfer

MRAM having two write conductors

Magnetic memory device

Triple sample sensing for magnetic random access memory (MRAM) with series diodes

Multiple buffer memory interface