Fishkill, New York
United States
58
2024-07-11
The entities that hold a legal rights for patent applications filed by inventor YOUNG Albert M.:
Albert M. YOUNG from Fishkill, US has applied for patents for these inventions. The list has both pending applications and granted patents:
SELF-ALIGNED ZERO TRACK SKIP
#2 | 2024-06-13POWER TAP CELL FOR FRONT SIDE POWER RAIL CONNECTION TO BSPDN
#3 | 2024-05-16BACKSIDE PROGRAMMABLE MEMORY
#4 | 2024-05-16SPACER CUT FOR ASYMMETRIC SOURCE/DRAIN EPITAXIAL STRUCTURE IN STACKED FET
#5 | 2024-05-16BACKSIDE PROGRAMMABLE GATE ARRAY
#6 | 2024-05-16STACKED FET WITH EXTREMELY SMALL CELL HEIGHT
#7 | 2024-04-25SELF-ALIGNED ZERO TRACK SKIP
#8 | 2024-01-11STACKED FIELD EFFECT TRANSISTOR CONTACTS
#9 | 2023-12-28SUBTRACTIVE SOURCE DRAIN CONTACT FOR STACKED DEVICES
#10 | 2023-12-28CONTACTS FOR STACKED FIELD EFFECT TRANSISTOR
#11 | 2023-12-28ENHANCED POWER AND SIGNAL FOR STACKED-FETS
#12 | 2023-12-21METHOD AND STRUCTURE OF FORMING INDEPENDENT CONTACT FOR STAGGERED CFET
#13 | 2023-12-14STACKED FIELD EFFECT TRANSISTOR
#14 | 2023-12-14HYBRID SIGNAL AND POWER TRACK FOR STACKED TRANSISTORS
#15 | 2023-11-30INTERCONNECT THROUGH GATE CUT FOR STACKED FET DEVICE
#16 | 2023-11-09Local interconnect for cross coupling
#17 | 2023-10-26CROSS-COUPLING CONNECTIONS FOR STACKED FIELD EFFECT TRANSISTORS
#18 | 2023-10-19STACKED FIELD-EFFECT TRANSISTORS HAVING LATCH CROSS-COUPLING CONNECTIONS
#19 | 2023-10-05High aspect ratio contact structure with multiple metal stacks
#20 | 2023-10-05Vertically-stacked field effect transistor cell
#21 | 2023-09-28BOTTOM CONTACT WITH SELF-ALIGNED SPACER FOR STACKED SEMICONDUCTOR DEVICES
#22 | 2023-07-06Static random access memory using vertical transport field effect transistors
#23 | 2023-06-29Backside power rails and power distribution network for density scaling
#24 | 2023-06-15Middle of line structure with stacked devices
#25 | 2023-06-08Staggered stacked semiconductor devices
#26 | 2023-03-23Backside electrical contacts to buried power rails
#27 | 2023-01-26Static random access memory using vertical transport field effect transistors
#28 | 2022-12-15Backside power rail integration
#29 | 2017-02-02Efficient voltage conversion
#30 | 2016-06-16Efficient voltage conversion
#31 | 2016-06-09OPTOELECTRONIC DETECTION SYSTEM
#32 | 2015-04-02OPTOELECTRONIC DETECTION SYSTEM
#33 | 2015-01-22Computer readable medium encoded with a program for fabricating 3D integrated circuit device using interface wafer as permanent carrier
#34 | 2013-07-25COMPUTER READABLE MEDIUM ENCODED WITH A PROGRAM FOR FABRICATING A 3D INTEGRATED CIRCUIT STRUCTURE
#35 | 2012-12-06Method for fabricating 3D integrated circuit device using interface wafer as permanent carrier
#36 | 2012-11-293D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer
#37 | 2012-07-26Optoelectronic detection system
#38 | 2012-07-05Method of forming adaptive interconnect structure having programmable contacts
#39 | 2011-10-13Bow-balanced 3D chip stacking
#40 | 2010-12-16Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer
#41 | 2010-10-28Adaptive interconnect structure
#42 | 2010-02-253D integrated circuit device fabrication using interface wafer as permanent carrier
#43 | 2009-12-17Programmable via structure and method of fabricating same
#44 | 2009-06-04Hermetic seal and reliable bonding structures for 3D applications
#45 | 2009-03-19Programmable via structure for three dimensional integration technology
#46 | 2008-10-30HERMETIC SEAL AND RELIABLE BONDING STRUCTURES FOR 3D APPLICATIONS
#47 | 2008-07-17Low-cost strained SOI substrate for high-performance CMOS technology
#48 | 2008-07-10THREE-DIMENSIONAL ARCHITECTURE FOR SELF-CHECKING AND SELF-REPAIRING INTEGRATED CIRCUITS
#49 | 2008-06-19Method and structure for optimizing yield of 3-D chip manufacture
#50 | 2008-06-19Hermetic seal and reliable bonding structures for 3D applications
#51 | 2008-06-19Programmable via structure and method of fabricating same
#52 | 2008-05-29HERMETIC SEAL AND RELIABLE BONDING STRUCTURES FOR 3D APPLICATIONS
#53 | 2008-03-20Wafer level I/O test, repair and/or customization enabled by I/O layer
#54 | 2008-01-10Optoelectronic detection system
#55 | 2007-10-11Programmable via structure for three dimensional integration technology
#56 | 2007-05-08Optoelectronic detection system
#57 | 2007-04-12Wafer level I/O test and repair enabled by I/O layer
#58 | 2007-04-12Method and structure for optimizing yield of 3-D chip manufacture
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