Inventor profile of:

ROBERT J. WENZEL

City:

Austin, Texas

Country:

United States

Published Applications:

17

Last publication date:

2017-05-04

Top Assignees for applications by ROBERT J. WENZEL

The entities that hold a legal rights for patent applications filed by inventor WENZEL ROBERT J.:

Recent patent applications by WENZEL ROBERT J.

ROBERT J. WENZEL from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2017-05-04
US20170125336A1
Electricity

Substrate with routing

#2 | 2013-08-01
US20130193589A1
Electricity

Packaged integrated circuit using wire bonds

#3 | 2010-04-01
US20100078760A1
Electricity

Integrated circuit module with integrated passive device

#4 | 2009-06-18
US20090152718A1
Electricity

Semiconductor die with die pad pattern

#5 | 2008-07-10
US20080164593A1
Electricity

Method of packaging semiconductor devices

#6 | 2008-06-19
US20080142960A1
Electricity

Circuit device with at least partial packaging and method for forming

#7 | 2008-06-12
US20080138938A1
Electricity

Die positioning for packaged integrated circuits

#8 | 2008-03-06
US20080057696A1
Electricity

Method of forming crack arrest features in embedded device build-up package and package thereof

#9 | 2007-12-13
US20070284711A1
Electricity

Methods and apparatus for thermal management in a multi-layer embedded chip structure

#10 | 2007-12-13
US20070284704A1
Electricity

Methods and apparatus for a semiconductor device package with improved thermal performance

#11 | 2007-09-13
US20070212813A1
Electricity

Perforated embedded plane package and method

#12 | 2007-05-10
US20070102828A1
Electricity

Fine pitch interconnect and method of making

#13 | 2006-08-31
US20060192301A1
Electricity

Semiconductor device with a protected active die region and method therefor

#14 | 2006-01-19
US20060012036A1
Electricity

Circuit device with at least partial packaging and method for forming

#15 | 2005-11-03
US20050242425A1
Electricity

Semiconductor device with a protected active die region and method therefor

#16 | 2005-07-26
US10418790
-

Circuit device with at least partial packaging, exposed active surface and a voltage reference plane

#17 | 2005-01-04
US10418763
-

Circuit device with at least partial packaging and method for forming

InventorID:

361380 ⎘