Ravi Kumar Arimilli

Event-based dynamic resource provisioning

Dynamic runtime modification of array layout for offset

Virtual controllers with a large data center

Bulk power assembly

Power conversion, control, and distribution system

Cache coherent I/O communication

Techniques for dynamically assigning jobs to processors in a cluster using local job tables

Techniques for dynamically assigning jobs to processors in a cluster based on inter-thread communications

Techniques for dynamically assigning jobs to processors in a cluster based on broadcast information

Techniques for dynamically assigning jobs to processors in a cluster based on processor workload

Multiprocessor system with retry-less TLBI protocol

Enhanced processor virtualization mechanism via saving and restoring soft processor/system states

Data processing system with backplane and processor books configurable to support both technical and commercial workloads

High speed memory cloning facility via a lockless multiprocessor mechanism

Method and data processing system for microprocessor communication using a processor interconnect in a multi-processor system

Enhanced processor virtualization mechanism via saving and restoring soft processor/system states

DATA PROCESSING SYSTEM WITH BACKPLANE AND PROCESSOR BOOKS CONFIGURABLE TO SUPPPRT BOTH TECHNICAL AND COMMERCIAL WORKLOADS

Method and data processing system for processor-to-processor communication in a clustered multi-processor system

System and method for completing full updates to entire cache lines stores with address-only bus operations

Method, processing unit and data processing system for microprocessor communication in a multi-processor system

Method and data processing system for microprocessor communication in a cluster-based multi-processor system

Method and data processing system for microprocessor communication in a cluster-based multi-processor system

Method and data processing system for microprocessor communication in a cluster-based multi-processor wireless network

Method, processing unit and data processing system for microprocessor communication in a multi-processor system

Cross partition sharing of state information

High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing system

Host Ethernet adapter for networking offload in server environment

Dynamic, Non-invasive detection of hot-pluggable problem components and re-active re-allocation of system resources from problem components

Managing processor architected state upon an interrupt

Data processing system and method with dynamic idle for tunable interface calibration

Multiprocessor system supporting multiple outstanding TLBI operations per partition

Method and data processing system for microprocessor communication in a cluster-based multi-processor network

Dynamic data routing mechanism for a high speed memory cloner

Data processing system providing hardware acceleration of input/output (I/O) communication

Programming means for dynamic specifications of cache management preferences

Robust system reliability via systolic manufacturing level chip test operating real time on microprocessors/systems

Data processing system having no system memory

Method, apparatus and system for managing released promotion bits

High speed memory cloning facility via a source/destination switching mechanism

Non-disruptive, dynamic hot-plug and hot-remove of server nodes in an SMP

High speed memory cloner within a data processing system

Imprecise cache line protection mechanism during a memory clone operation

Dynamically managing saved processor soft states

Processor virtualization mechanism via an enhanced restoration of hard architected states

Acceleration of input/output (I/O) communication through improved address translation

Layered local cache with lower level cache optimizing allocation mechanism

System and method for completing updates to entire cache lines with address-only bus operations

System and method to stall dispatch of gathered store operations in a store queue using a timer

System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture

Asynchronous non-blocking snoop invalidation

System bus read data transfers with data ordering control bits

Data processing system with naked cache line write operations

Method, apparatus and system for accessing a global promotion facility through execution of a branch-type instruction

Method and system of managing virtualized physical memory in a data processing system

Method, apparatus and system that cache promotion information within a processor separate from instructions and data

Method and data processing system having dynamic profile-directed feedback at runtime

Method and data processing system optimizing performance through reporting of thread-level hardware resource utilization

Multiprocessor data processing system having scalable data interconnect and data routing mechanism

Multiprocessor data processing system having a data routing mechanism regulated through control communication

High speed memory cloning facility via a coherently done mechanism

Method and apparatus for transmitting packets within a symmetric multiprocessor system

Method and system for thread-based memory speculation in a memory subsystem of a data processing system

Method and system for supplier-based memory speculation in a memory subsystem of a data processing system

Method and system of managing virtualized physical memory in a memory controller and processor system

Method and system of managing virtualized physical memory in a multi-processor system

Memory directory management in a multi-node computer system

Dynamic software accessibility to a microprocessor system with a high speed memory cloner

High speed memory cloner with extended cache coherency protocols and responses

Dynamic history based mechanism for the granting of exclusive data ownership in a non-uniform memory access (NUMA) computer system

Speculative execution of instructions and processes before completion of preceding barrier operations

System bus read data transfers with data ordering control bits

Data processing system having a physically addressed cache of disk memory

Robust system bus recovery

Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response

Method, apparatus and system for acquiring a plurality of global promotion facilities through execution of an instruction