Inventor profile of:

Kenneth Lee Wright

City:

Austin, Texas

Country:

United States

Published Applications:

19

Last publication date:

2010-06-24

Top Assignees for applications by Kenneth Lee Wright

The entities that hold a legal rights for patent applications filed by inventor Wright Kenneth Lee:

Recent patent applications by Wright Kenneth Lee

Kenneth Lee Wright from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2010-06-24
US20100162037A1
Physics

Memory System having Spare Memory Devices Attached to a Local Interface Bus

#2 | 2009-02-17
US10318515
-

Method and data processing system for microprocessor communication using a processor interconnect in a multi-processor system

#3 | 2008-06-26
US20080155231A1
Physics

Method and data processing system for processor-to-processor communication in a clustered multi-processor system

#4 | 2008-05-08
US20080109816A1
Physics

Method, processing unit and data processing system for microprocessor communication in a multi-processor system

#5 | 2008-04-17
US20080091918A1
Electricity

Method and data processing system for microprocessor communication in a cluster-based multi-processor system

#6 | 2008-04-15
US10318516
-

Method and data processing system for microprocessor communication in a cluster-based multi-processor system

#7 | 2008-04-15
US10318513
-

Method and data processing system for microprocessor communication in a cluster-based multi-processor wireless network

#8 | 2008-04-08
US10318514
-

Method, processing unit and data processing system for microprocessor communication in a multi-processor system

#9 | 2007-04-12
US20070083717A1
Physics

Chained cache coherency states for sequential homogeneous access to a cache line with outstanding data response

#10 | 2007-04-12
US20070083716A1
Physics

Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response

#11 | 2007-03-20
US10422677
-

Localized cache block flush instruction

#12 | 2006-08-10
US20060179185A1
Physics

Method to preserve ordering of read and write operations in a DMA system by delaying read access

#13 | 2006-03-21
US10319023
-

Data processing system having no system memory

#14 | 2005-08-23
US9671513
-

Bi-directional stack in a linear memory array

#15 | 2005-07-19
US10268741
-

Method and system of managing virtualized physical memory in a data processing system

#16 | 2005-06-14
US10268728
-

Method and system of managing virtualized physical memory in a memory controller and processor system

#17 | 2005-06-07
US10268743
-

Method and system of managing virtualized physical memory in a multi-processor system

#18 | 2005-03-31
US20050071573A1
Physics

Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes

#19 | 2005-03-10
US20050055528A1
Physics

Data processing system having a physically addressed cache of disk memory

InventorID:

3633849 ⎘