Austin, Texas
United States
104
2010-10-14
The entities that hold a legal rights for patent applications filed by inventor Williams Derek Edward:
Derek Edward Williams from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Processor system and methods of triggering a block move using a system bus write command initiated by user code
#2 | 2010-10-14Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipeline
#3 | 2009-07-30Tracking converge results in a batch simulation farm network
#4 | 2009-02-19Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing
#5 | 2009-02-17Method and data processing system for microprocessor communication using a processor interconnect in a multi-processor system
#6 | 2008-11-27Program product providing a configuration specification language having clone latch support
#7 | 2008-11-20METHOD, SYSTEM AND PROGRAM PRODUCT SUPPORTING USER TRACING IN A SIMULATOR
#8 | 2008-10-16Program product for providing a configuration specification language supporting incompletely specified configuration entities
#9 | 2008-10-16Controlling operation of a digital system utilizing register entities
#10 | 2008-10-09Program product for defining and recording minimum and maximum event counts of a simulation utilizing a high level language
#11 | 2008-09-25Configuration specification language supporting arbitrary mapping functions for configuration constructs
#12 | 2008-09-25Variable store gather window
#13 | 2008-07-24Annotating system traces with control program information and presenting annotated system traces
#14 | 2008-07-10Method and system for reducing storage requirements of simulation data via KEYWORD restrictions
#15 | 2008-07-03METHOD, SYSTEM AND PROGRAM PRODUCT PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE SUPPORTING ARBITRARY MAPPING FUNCTIONS FOR CONFIGURATION CONSTRUCTS
#16 | 2008-06-26Method and data processing system for processor-to-processor communication in a clustered multi-processor system
#17 | 2008-06-12Method for Priority Scheduling and Priority Dispatching of Store Conditional Operations in a Store Queue
#18 | 2008-06-12System and method for completing full updates to entire cache lines stores with address-only bus operations
#19 | 2008-06-12Method for priority scheduling and priority dispatching of store conditional operations in a store queue
#20 | 2008-05-13Method and system for reducing storage requirements of simulation data via keyword restrictions
#21 | 2008-05-08Method, processing unit and data processing system for microprocessor communication in a multi-processor system
#22 | 2008-04-24Data processing system and method for efficient L3 cache directory management
#23 | 2008-04-17Method and data processing system for microprocessor communication in a cluster-based multi-processor system
#24 | 2008-04-17Data processing system and method for efficient L3 cache directory management
#25 | 2008-04-15Method and data processing system for microprocessor communication in a cluster-based multi-processor system
#26 | 2008-04-15Method and data processing system for microprocessor communication in a cluster-based multi-processor wireless network
#27 | 2008-04-15Tracking converage results in a batch simulation farm network
#28 | 2008-04-10Processor and data processing system employing a variable store gather window
#29 | 2008-04-08Method, processing unit and data processing system for microprocessor communication in a multi-processor system
#30 | 2008-03-27Method, system and program product supporting presentation of a simulated or hardware system including configuration entities
#31 | 2008-02-14Data processing system and method for efficient communication utilizing an Tn and Ten coherency states
#32 | 2008-01-24Presentation of a simulated or hardware system including configuration entities
#33 | 2007-11-29Variable store gather window
#34 | 2007-10-04Configuration database supporting selective presentation of configuration entities
#35 | 2007-09-04Method, system and program product for determining a configuration of a digital design by reference to an invertible configuration database
#36 | 2007-07-26Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs
#37 | 2007-05-01High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing system
#38 | 2007-04-17C-API instrumentation for HDL models
#39 | 2007-04-12Chained cache coherency states for sequential homogeneous access to a cache line with outstanding data response
#40 | 2007-04-12Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response
#41 | 2007-04-10Method and system for selectively storing and retrieving simulation data utilizing keywords
#42 | 2007-03-20Method and system for reducing storage and transmission requirements for simulation results
#43 | 2007-03-01Method, system and program product for specifying and using register entities to configure a simulated or physical digital system
#44 | 2007-01-23Method, system and program product for implementing a read-only dial in a configuration database of a digital design
#45 | 2007-01-09Method, system and program product for configuring a simulation model of a digital design
#46 | 2007-01-02Dynamic loading of C-API HDL model instrumentation
#47 | 2006-12-05Method, system and program product that utilize a configuration database to configure a hardware digital system having an arbitrary system size and component set
#48 | 2006-11-28Maintaining data integrity within a distributed simulation environment
#49 | 2006-11-28Non-redundant collection of harvest events within a batch simulation farm network
#50 | 2006-11-07Method, system and program product for specifying a configuration for multiple signal or dial instances in a digital system
#51 | 2006-10-19Cache memory, processing unit, data processing system and method for assuming a selected invalid coherency state based upon a request source
#52 | 2006-08-24Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs
#53 | 2006-08-17Cache memory direct intervention
#54 | 2006-08-15Annealing harvest event testcase collection within a batch simulation farm
#55 | 2006-08-15Signal override for simulation models
#56 | 2006-08-10Data processing system and method for efficient L3 cache directory management
#57 | 2006-08-10Data processing system and method for efficient communication utilizing an Tn and Ten coherency states
#58 | 2006-08-10System and method of re-ordering store operations within a processor
#59 | 2006-08-01Count data access in a distributed simulation environment
#60 | 2006-07-18Method, system and program product for specifying a configuration of a digital system described by a hardware description language (HDL) model
#61 | 2006-07-18Method, system and program product for automatically transforming a configuration of a digital system utilizing traceback of signal states
#62 | 2006-07-04Method and data processing system for microprocessor communication in a cluster-based multi-processor network
#63 | 2006-06-13Method, system and program product that utilize a configuration database to configure a hardware digital system having multiple access methods
#64 | 2006-06-13Method, system and program product for specifying and using a dial having a default value to configure a digital system described by a hardware description language (HDL) model
#65 | 2006-06-08Method, system and program product for defining and recording threshold-qualified count events of a simulation by testcases
#66 | 2006-05-30Integrated purge store mechanism to flush L2/L3 cache structure for improved reliabity and serviceability
#67 | 2006-05-04Processor, method, and data processing system employing a variable store gather window
#68 | 2006-05-02Method, system and program product for specifying and using dials having phased default values to configure a simulated or physical digital system
#69 | 2006-05-02Naming and managing simulation model events
#70 | 2006-04-27Method for priority scheduling and priority dispatching of store conditional operations in a store queue
#71 | 2006-04-27Method, system and program product for defining and recording minimum and maximum event counts of a simulation utilizing a high level language
#72 | 2006-04-27Method, system and program product for defining and recording minimum and maximum count events of a simulation
#73 | 2006-04-20Processor, data processing system and method for synchronzing access to data in shared memory
#74 | 2006-04-20Processor, data processing system and method for synchronizing access to data in shared memory
#75 | 2006-04-20Processor, data processing system and method for synchronizing access to data in shared memory
#76 | 2006-04-11Centralized disablement of instrumentation events within a batch simulation farm network
#77 | 2006-03-21Method, apparatus and system for managing released promotion bits
#78 | 2006-02-02Method, system and program product for providing a configuration specification language supporting selective presentation of configuration entities
#79 | 2006-02-02Method, system and program product supporting presentation of a simulated or hardware system including configuration entities
#80 | 2006-01-31Method, system and program product for specifying a dial group for a digital system described by a hardware description language (HDL) model
#81 | 2006-01-19Methods, systems and program products for annotating system traces with control program information and presenting annotated system traces
#82 | 2006-01-05Method, system and program product for providing a configuration specification language supporting incompletely specified configuration entities
#83 | 2005-12-20Embedded hardware description language instrumentation
#84 | 2005-12-15Method, system and program product for specifying and using register entities to configure a simulated or physical digital system
#85 | 2005-11-10System and method for completing updates to entire cache lines with address-only bus operations
#86 | 2005-11-10System and method to stall dispatch of gathered store operations in a store queue using a timer
#87 | 2005-11-08System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture
#88 | 2005-09-27System and method for reducing contention in a multi-sectored cache
#89 | 2005-09-06Method, system and program product for reducing a size of a configuration database utilized to configure a hardware digital system
#90 | 2005-09-06Hierarchical processing of simulation model events
#91 | 2005-08-23Fail thresholding in a batch simulation farm network
#92 | 2005-08-02Method, apparatus and system for accessing a global promotion facility through execution of a branch-type instruction
#93 | 2005-07-19Method, apparatus and system that cache promotion information within a processor separate from instructions and data
#94 | 2005-07-19Detecting events within simulation models
#95 | 2005-07-07Method, system and program product providing a configuration specification language having split latch support
#96 | 2005-07-07Method, system and program product providing a configuration specification language supporting arbitrary mapping functions for configuration constructs
#97 | 2005-07-07Method and system for selective compilation of instrumentation entities into a simulation model of a digital design
#98 | 2005-07-07Method, system and program product supporting user tracing in a simulator
#99 | 2005-05-03System and method for exposing hidden events on system buses
#100 | 2005-04-12Speculative execution of instructions and processes before completion of preceding barrier operations
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