John E. Barth, JR.

Array organization and architecture to perform range-match operations with content addressable memory (CAM) circuits

Providing transposable access to a synapse array using a recursive array layout

Array of processor core circuits with reversible tiers

Vertically integrated memory cell

Faulty core recovery mechanisms for a three-dimensional network on a processor array

Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array

Vertical fin eDRAM

Faulty core recovery mechanisms for a three-dimensional network on a processor array

Array organization and architecture to perform range-match operations with content addressable memory (CAM) circuits

Dummy gate structure for electrical isolation of a fin DRAM

Dynamic random access memory cell with self-aligned strap

Providing transposable access to a synapse array using a recursive array layout

Vertically integrated memory cell

Providing transposable access to a synapse array using a recursive array layout

Dummy gate structure for electrical isolation of a fin DRAM

Dynamic random access memory cell with self-aligned strap

Array organization and architecture to perform range-match operations with content addressable memory (CAM) circuits

Gated-feedback sense amplifier for single-ended local bit-line memories

Electronic circuit for fitting a virtual address range to a physical memory containing faulty address

Metal-insulator-metal (MIM) capacitor with deep trench (DT) structure and method in a silicon-on-insulator (SOI)

Providing transposable access to a synapse array using column aggregation

Reduced stress high voltage word line driver

Electronic circuit for remapping faulty memory arrays of variable size

Signal margin centering for single-ended eDRAM sense amplifier

Array of processor core circuits with reversible tiers

Complementary metal-oxide-semiconductor (CMOS) dynamic random access memory (DRAM) cell with sense amplifier

Semiconductor-on-oxide structure and method of forming

Final faulty core recovery mechanisms for a two-dimensional network on a processor array

Faulty core recovery mechanisms for a three-dimensional network on a processor array

Semiconductor-on-insulator (SOI) deep trench capacitor

Metal-insulator-metal (MIM) capacitor with deep trench (DT) structure and method in a silicon-on-insulator (SOI)

MEMORY DEVICE SUPPORT OF DYNAMICALLY CHANGING FREQUENCY IN MEMORY SYSTEMS

Semiconductor-on-oxide structure and method of forming

Creating deep trenches on underlying substrate

Sense amplifier having an isolated pre-charge architecture, a memory circuit incorporating such a sense amplifier and associated methods

FET eDRAM trench self-aligned to buried strap

Integrated circuits comprising an active transistor electrically connected to a trench capacitor by an overlying contact

Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices

VDD pre-set of direct sense DRAM

Embedded dynamic random access memory device and method

Deep trench capacitor for SOI CMOS devices for soft error immunity

SOI body contact using E-DRAM technology

Capacitively isolated mismatch compensated sense amplifier

Vertical through-silicon via for a semiconductor structure

Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices

SOI body contact using E-DRAM technology

Integrated circuits comprising an active transistor electrically connected to a trench capacitor by an overlying contact and methods of making

SYSTEM TO EVALUATE CHARGE PUMP OUTPUTS AND ASSOCIATED METHODS

SYSTEM TO GENERATE A REFERENCE FOR A CHARGE PUMP AND ASSOCIATED METHODS

Dynamic random access memory circuit, design structure and method

Soft error protection structure employing a deep trench

DESIGN STRUCTURE FOR AN EMBEDDED DRAM HAVING MULTI-USE REFRESH CYCLES

EMBEDDED DRAM HAVING MULTI-USE REFRESH CYCLES

Design structure including failing address register and compare logic for multi-pass repair of memory arrays

FAILING ADDRESS REGISTER AND COMPARE LOGIC FOR MULTI-PASS REPAIR OF MEMORY ARRAYS

APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS

Method and system for implementing dynamic refresh protocols for DRAM based cache

STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS

Design structure for low overhead switched header power savings apparatus

Low overhead switched header power savings apparatus

Memory cell access circuit

Low overhead switched header power savings apparatus

Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices

Memory cell access circuit

System and method for capacitive mis-match bit-line sensing

ECC based system and method for repairing failed memory elements

Low-cost deep trench decoupling capacitor device and process of manufacture

Bi-mode sense amplifier with dual utilization of the reference cells and dual precharge scheme for improving data retention

Bitline twisting structure for memory arrays incorporating reference wordlines

Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices

Concurrent refresh mode with distributed row address counters in an embedded DRAM

Method for separating shift and scan paths on scan-only, single port LSSD latches

System and method for implementing self-timed decoded data paths in integrated circuits

Method for reduced electrical fusing time