Sunnyvale, California
United States
26
2018-04-19
The entities that hold a legal rights for patent applications filed by inventor Bulucea Constantin:
Constantin Bulucea from Sunnyvale, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Structures to avoid floating resurf layer in high voltage lateral devices
#2 | 2016-09-01Structures to avoid floating RESURF layer in high voltage lateral devices
#3 | 2014-04-10Dielectrically Terminated Superjunction FET
#4 | 2013-05-23Configuration and fabrication of semiconductor structure using empty and filled wells
#5 | 2013-01-17Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone
#6 | 2012-11-13Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications
#7 | 2012-10-18Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses
#8 | 2012-07-19Configuration and fabrication of semiconductor structure in which source and drain extensions of field-effect transistor are defined with different dopants
#9 | 2012-07-19Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications
#10 | 2012-07-19Configuration and fabrication of semiconductor structure having bipolar junction transistor in which non-monocrystalline semiconductor spacing portion controls base-link length
#11 | 2012-06-07STATIC INDUCTION TRANSISTOR WITH DIELECTRIC CARRIER SEPARATION LAYER
#12 | 2012-04-26Group III-nitride HEMT with multi-layered substrate having a second layer of one conductivity type touching a top surface of a first layers of different conductivity type and a method for forming the same
#13 | 2012-04-26Group III-nitride HEMT having a well region formed on the surface of substrate and contacted the buffer layer to increase breakdown voltage and the method for forming the same
#14 | 2011-10-11Fabrication of field-effect transistor having hypoabrupt body dopant distribution below source/drain zone
#15 | 2011-07-05Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications
#16 | 2010-09-30Configuration and fabrication of semiconductor structure having extended-drain field-effect transistor
#17 | 2010-09-30Structure and fabrication of field-effect transistor having source/drain extension defined by multiple local concentration maxima
#18 | 2010-09-30Semiconductor structure in which source and drain extensions of field-effect transistor are defined with different dopants
#19 | 2010-09-30Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses
#20 | 2010-09-30Fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone
#21 | 2010-09-30Configuration and fabrication of semiconductor structure having bipolar junction transistor in which non-monocrystalline semiconductor spacing portion controls base-link length
#22 | 2010-09-30Asymmetric field-effect transistor having asymmetric channel zone and differently configured source/drain extensions
#23 | 2010-09-30Structure and fabrication of field-effect transistor using empty well in combination with source/drain extensions or/and halo pocket
#24 | 2010-09-30Configuration and fabrication of semiconductor structure using empty and filled wells
#25 | 2010-09-30Fabrication of asymmetric field-effect transistors using L-shaped spacers
#26 | 2008-12-18Fabrication of semiconductor architecture having field-effect transistors especially suitable for analog applications
36802 ⎘