Inventor profile of:

Peter H. Mitchell

City:

Jericho, Vermont

Country:

United States

Published Applications:

47

Last publication date:

2024-03-21

Top Assignees for applications by Peter H. Mitchell

The entities that hold a legal rights for patent applications filed by inventor Mitchell Peter H.:

Recent patent applications by Mitchell Peter H.

Peter H. Mitchell from Jericho, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2024-03-21
US20240097065A1
Electricity

Thin single-crystal silicon solar cells mounted to a structural support member and method of fabricating

#2 | 2020-03-17
US16173680
Performing operations; transporting

Method of cleaving a single crystal substrate parallel to its active planar surface and method of using the cleaved daughter substrate

#3 | 2010-10-28
US20100273298A1
Electricity

Method of making integrated circuit chip utilizing oriented carbon nanotube conductive layers

#4 | 2008-10-23
US20080261363A1
Electricity

Method of forming a dual gated FinFET gain cell

#5 | 2008-09-18
US20080227264A1
Electricity

Vertical nanotube semiconductor device structures and methods of forming the same

#6 | 2008-08-28
US20080206937A1
Electricity

Methods for forming a wrap-around gate field effect transistor

#7 | 2008-08-21
US20080197448A1
Electricity

SHALLOW TRENCH ISOLATION FILL BY LIQUID PHASE DEPOSITION OF SiO2

#8 | 2008-07-10
US20080165335A1
Physics

Immersion lithography with equalized pressure on at least projection optics component and wafer

#9 | 2008-07-03
US20080160312A1
Performing operations; transporting

Methods and structures for promoting stable synthesis of carbon nanotubes

#10 | 2008-02-21
US20080044954A1
Electricity

Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby

#11 | 2008-02-21
US20080042287A1
Electricity

Integrated circuit chip utilizing oriented carbon nanotube conductive layers

#12 | 2008-02-14
US20080040696A1
Physics

Design Structures Incorporating Shallow Trench Isolation Filled by Liquid Phase Deposition of SiO2

#13 | 2007-12-27
US20070296937A1
Physics

ILLUMINATION LIGHT IN IMMERSION LITHOGRAPHY STEPPER FOR PARTICLE OR BUBBLE DETECTION

#14 | 2007-10-04
US20070228510A1
Electricity

Shallow trench isolation fill by liquid phase deposition of SiO

#15 | 2007-08-09
US20070184647A1
Performing operations; transporting

Integrated Circuit Chip Utilizing Dielectric Layer Having Oriented Cylindrical Voids Formed from Carbon Nanotubes

#16 | 2007-08-09
US20070184588A1
Electricity

Methods for forming a wrap-around gate field effect transistor

#17 | 2007-03-01
US20070048879A1
Electricity

Method for making integrated circuit chip utilizing oriented carbon nanotube conductive layers

#18 | 2006-12-28
US20060292861A1
Performing operations; transporting

Method for making integrated circuit chip having carbon nanotube composite interconnection vias

#19 | 2006-12-28
US20060289794A1
Physics

Immersion lithography with equalized pressure on at least projection optics component and wafer

#20 | 2006-08-03
US20060172496A1
Electricity

Double-gate FETs (Field Effect Transistors)

#21 | 2006-08-03
US20060169972A1
Electricity

Vertical carbon nanotube transistor integration

#22 | 2006-06-15
US20060128137A1
Performing operations; transporting

Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes

#23 | 2006-03-23
US20060060562A1
Electricity

Sub-lithographic imaging techniques and processes

#24 | 2006-02-02
US20060022221A1
Electricity

Integrated circuit chip utilizing oriented carbon nanotube conductive layers

#25 | 2006-01-12
US20060008927A1
Electricity

Method of forming a dual gated FinFET gain cell

#26 | 2005-12-29
US20050286293A1
Physics

Horizontal memory gain cells

#27 | 2005-12-01
US20050266627A1
Electricity

Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage

#28 | 2005-11-29
US10879833
-

Dual gated finfet gain cell

#29 | 2005-10-27
US20050237501A1
Physics

Wafer cell for immersion lithography

#30 | 2005-09-29
US20050213061A1
Physics

System and apparatus for photolithography

#31 | 2005-09-15
US20050202607A1
Electricity

Method of forming FinFET gates without long etches

#32 | 2005-09-15
US20050202322A1
Physics

Methods of forming alternating phase shift masks having improved phase-shift tolerance

#33 | 2005-09-01
US20050189655A1
Performing operations; transporting

Integrated circuit chip utilizing carbon nanotube composite interconnection vias

#34 | 2005-08-18
US20050179029A1
Electricity

Vertical carbon nanotube field effect transistors and arrays

#35 | 2005-08-04
US20050167740A1
Electricity

Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage

#36 | 2005-08-04
US20050167655A1
Electricity

Vertical nanotube semiconductor device structures and methods of forming the same

#37 | 2005-07-21
US20050158673A1
Physics

Liquid-filled balloons for immersion lithography

#38 | 2005-07-07
US20050145838A1
Electricity

Vertical Carbon Nanotube Field Effect Transistor

#39 | 2005-07-07
US20050145803A1
Physics

Moving lens for immersion optical lithography

#40 | 2005-06-16
US20050130387A1
Electricity

Shallow trench isolation fill by liquid phase deposition of SiO2

#41 | 2005-06-16
US20050130341A1
Electricity

Selective synthesis of semiconducting carbon nanotubes

#42 | 2005-06-16
US20050129948A1
Performing operations; transporting

Methods and structures for promoting stable synthesis of carbon nanotubes

#43 | 2005-06-16
US20050127466A1
Electricity

Wrap-around gate field effect transistor

#44 | 2005-05-19
US20050106472A1
Physics

Alternating phase mask built by additive film deposition

#45 | 2005-05-10
US10454852
-

Method for supporting a bond pad in a multilevel interconnect structure and support structure formed thereby

#46 | 2005-04-28
US20050087875A1
Electricity

Method of forming gas dielectric with support structure

#47 | 2005-04-05
US10760500
-

Method for forming quadruple density sidewall image transfer (SIT) structures

InventorID:

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