Hornitos, California
United States
98
2023-11-30
The entities that hold a legal rights for patent applications filed by inventor Crisp Richard Dewitt:
Richard Dewitt Crisp from Hornitos, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Low-Pincount High-Bandwidth Memory And Memory Bus
#2 | 2021-09-23Low-pincount high-bandwidth memory and memory bus
#3 | 2020-09-24Low-pincount high-bandwidth memory and memory bus
#4 | 2020-04-23Superscalar Memory IC, Bus And System For Use Therein
#5 | 2019-10-03Low-pincount high-bandwidth memory and memory bus
#6 | 2019-01-31Microelectronic package including microelectronic elements having stub minimization for wirebond assemblies without windows
#7 | 2018-11-15Microelectronic package having stub minimization using symmetrically-positioned duplicate sets of terminals for wirebond assemblies without windows
#8 | 2018-01-25FLIP-CHIP, FACE-UP AND FACE-DOWN CENTERBOND MEMORY WIREBOND ASSEMBLIES
#9 | 2017-12-21Low-pincount high-bandwidth memory and memory bus
#10 | 2017-09-07Microelectronic package including microelectronic elements having stub minimization for wirebond assemblies without windows
#11 | 2017-03-23STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE
#12 | 2017-03-02Microelectronic package having stub minimization using symmetrically-positioned duplicate sets of terminals for wirebond assemblies without windows
#13 | 2017-01-26Microelectronic element with bond elements to encapsulation surface
#14 | 2016-09-22Microelectronic package having at least two microelectronic elements that are horizontally spaced apart from each other
#15 | 2016-09-15Stub minimization for assemblies without wirebonds to package substrate
#16 | 2016-09-08MICROELECTRONIC PACKAGE WITH CONSOLIDATED CHIP STRUCTURES
#17 | 2016-07-07Microelectronic assembly with opposing microelectronic packages each having terminals with signal assignments that mirror each other with respect to a central axis
#18 | 2016-06-30Microelectronic packaging without wirebonds to package substrate having terminals with signal assignments that mirror each other with respect to a central axis
#19 | 2016-06-16Memory module in a package
#20 | 2016-03-31Stub minimization using duplicate sets of signal terminals
#21 | 2016-02-04Reconfigurable PoP
#22 | 2015-12-24Microelectronic package with consolidated chip structures
#23 | 2015-12-17Co-support for XFD packaging
#24 | 2015-10-22Single package dual channel memory with co-support
#25 | 2015-08-27Multiple die in a face down package
#26 | 2015-08-06Multiple die face-down stacking for two or more die
#27 | 2015-07-30Microelectronic unit and package with positional reversal
#28 | 2015-07-16Stub minimization for multi-die wirebond assemblies with parallel windows
#29 | 2015-06-25Stub minimization with terminal grids offset from center of package
#30 | 2015-05-28Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
#31 | 2015-04-30Flip-chip, face-up and face-down centerbond memory wirebond assemblies
#32 | 2015-04-30Co-support for XFD packaging
#33 | 2015-03-19MICROELECTRONIC ELEMENT WITH BOND ELEMENTS TO ENCAPSULATION SURFACE
#34 | 2015-02-12ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS AND IMPROVED GROUND OR POWER DISTRIBUTION
#35 | 2014-12-18Memory module in a package
#36 | 2014-12-11Single package dual channel memory with co-support
#37 | 2014-11-13Power boosting circuit for semiconductor packaging
#38 | 2014-11-06Stub minimization for multi-die wirebond assemblies with parallel windows
#39 | 2014-11-06Microelectronic assembly including memory packages connected to circuit panel, the memory packages having stub minimization for wirebond assemblies without windows
#40 | 2014-10-02Impedance controlled packages with metal sheet or 2-layer rdl
#41 | 2014-09-18Manufacture of face-down microelectronic packages
#42 | 2014-09-18In-package fly-by signaling
#43 | 2014-08-28Microelectronic package with consolidated chip structures
#44 | 2014-08-28Enhanced stacked microelectronic assemblies with central contacts
#45 | 2014-08-28Microelectronic unit and package with positional reversal
#46 | 2014-07-22Reconfigurable pop
#47 | 2014-07-03Stub minimization using duplicate sets of signal terminals
#48 | 2014-06-19Stub minimization using duplicate sets of signal terminals having modulo-x symmetry in assemblies without wirebonds to package substrate
#49 | 2014-06-19Stub minimization using duplicate sets of terminals having modulo-x symmetry for wirebond assemblies without windows
#50 | 2014-05-13In-package fly-by signaling
#51 | 2014-05-01Multiple die in a face down package
#52 | 2014-04-24Co-support circuit panel and microelectronic packages
#53 | 2014-04-17Stub minimization for assemblies without wirebonds to package substrate
#54 | 2014-02-27Co-support component and microelectronic assembly
#55 | 2014-02-27Co-support module and microelectronic assembly
#56 | 2014-02-27Co-support system and microelectronic assembly
#57 | 2014-02-13Flip-chip, face-up and face-down wirebond combination package
#58 | 2014-02-06Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
#59 | 2013-11-21Deskewed multi-die packages
#60 | 2013-11-14Lead structures with vertical offsets
#61 | 2013-10-31Stub minimization using duplicate sets of signal terminals
#62 | 2013-05-23Multiple die face-down stacking for two or more die
#63 | 2013-04-04Stub minimization with terminal grids offset from center of package
#64 | 2013-04-04Stub minimization for multi-die wirebond assemblies with parallel windows
#65 | 2013-04-04Stub minimization for assemblies without wirebonds to package substrate
#66 | 2013-04-04Stub minimization for wirebond assemblies without windows
#67 | 2013-04-04Stub minimization for wirebond assemblies without windows
#68 | 2013-04-04Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
#69 | 2013-04-04Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
#70 | 2013-04-04Stub minimization for multi-die wirebond assemblies with parallel windows
#71 | 2013-04-04Stub minimization for wirebond assemblies without windows
#72 | 2013-04-04Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
#73 | 2013-04-04Stub minimization for assemblies without wirebonds to package substrate
#74 | 2013-04-04Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
#75 | 2013-04-04Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
#76 | 2013-04-04Stub minimization for assemblies without wirebonds to package substrate
#77 | 2013-04-04Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
#78 | 2013-03-07Flip-chip, face-up and face-down wirebond combination package
#79 | 2013-02-21Power boosting circuit for semiconductor packaging
#80 | 2013-02-21Multiple die in a face down package
#81 | 2013-01-17Memory module in a package
#82 | 2013-01-17Memory module in a package
#83 | 2013-01-17De-skewed multi-die packages
#84 | 2013-01-01Stub minimization for multi-die wirebond assemblies with parallel windows
#85 | 2012-12-13Impedence controlled packages with metal sheet or 2-layer RDL
#86 | 2012-10-25Multiple die face-down stacking for two or more die
#87 | 2012-10-25Flip-chip, face-up and face-down wirebond combination package
#88 | 2012-10-25Flip-chip, face-up and face-down centerbond memory wirebond assemblies
#89 | 2012-10-02Stub minimization for multi-die wirebond assemblies with orthogonal windows
#90 | 2012-08-28Stub minimization for multi-die wirebond assemblies with orthogonal windows
#91 | 2012-06-21Enhanced stacked microelectronic assemblies with central contacts
#92 | 2012-06-21Enhanced stacked microelectronic assemblies with central contacts and improved ground or power distribution
#93 | 2012-06-21Enhanced stacked microelectronic assemblies with central contacts and improved ground or power distribution
#94 | 2012-04-19Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
#95 | 2012-03-22Metal can impedance control structure
#96 | 2012-03-22Impedance controlled packages with metal sheet or 2-layer RDL
#97 | 2010-03-04Wafer level compliant packages for rear-face illuminated solid state image sensors
#98 | 2009-08-27WAFER LEVEL PACKAGES FOR REAR-FACE ILLUMINATED SOLID STATE IMAGE SENSORS
36913 ⎘