Anthony K. Stamper

Contact-over-active-gate transistor structures with contacts landed on enlarged gate portions

Bulk substrates with a self-aligned buried polycrystalline layer

Gate contacts with airgap isolation

Semiconductor device structures with a substrate biasing scheme

Isolation trenches augmented with a trap-rich layer

III-V compound semiconductor layer stacks with electrical isolation provided by a trap-rich layer

Field-effect transistors with a polycrystalline body in a shallow trench isolation region

Epitaxial growth constrained by a template

Trap-rich layer in a high-resistivity semiconductor layer

Buried damage layers for electrical isolation

Trench-based photodiodes

Photodetectors with a lateral composition gradient

Multi-depth regions of high resistivity in a semiconductor substrate

Complementary transistor structures formed with the assistance of doped-glass layers

Bulk substrates with a self-aligned buried polycrystalline layer

Semiconductor structures including stacked depleted and high resistivity regions

Photodiodes integrated into a BiCMOS process

Fin-type field-effect transistors over one or more buried polycrystalline layers

Field-effect transistors with vertically-serpentine gates

Field-effect transistors with laterally-serpentine gates

Heterojunction bipolar transistors having bases with different elevations

Substrates with self-aligned buried dielectric and polycrystalline layers

Optical beam steering with directionality provided by switched grating couplers

Optical switches and routers operated by phase-changing materials controlled by heaters

Bulk substrates with a self-aligned buried polycrystalline layer

Structures with an airgap and methods of forming such structures

DEVICE STRUCTURES FORMED WITH A SILICON-ON-INSULATOR SUBSTRATE THAT INCLUDES A TRAP-RICH LAYER

Chip package with emitter finger cells spaced by different spacings from a heat sink to provide reduced temperature variation

Backside contact to a final substrate

Hybrid cascode constructions with multiple transistor types

Bulk substrates with a self-aligned buried polycrystalline layer

Shallow trench isolation formation without planarization

Backside contact to a final substrate

TRENCH ISOLATION FORMATION FROM THE SUBSTRATE BACK SIDE USING LAYER TRANSFER

Backside device contact

Backside device contact

Backside device contact

Backside contact to a final substrate

Backside contact to a final substrate

Backside contact to a final substrate

SOI wafers with buried dielectric layers to prevent CU diffusion

Device layer transfer with a preserved handle wafer section

Backside integration of RF filters for RF front end modules and design structure

SOI wafers with buried dielectric layers to prevent Cu diffusion

Semiconductor structures having low resistance paths throughout a wafer

Backside contact to a final substrate

Backside contact to a final substrate

Device structures for a silicon-on-insulator substrate with a high-resistance handle wafer

Bipolar junction transistors with double-tapered emitter fingers

Backside device contact

CHIP PACKAGES WITH REDUCED TEMPERATURE VARIATION

Backside contact to final substrate

Edge trim processes and resultant structures

On chip antenna with opening

Electronic package that includes a plurality of integrated circuit devices bonded in a three-dimensional stack arrangement

Wafer with plated wires and method of fabricating same

Semiconductor structures having low resistance paths throughout a wafer

Backside device contact

Replacement emitter for reduced contact resistance

Titanium tungsten liner used with copper interconnects

Tunable scaling of current gain in bipolar junction transistors

High resistivity substrate final resistance test structure

Contact module for optimizing emitter and contact resistance

Microbolometer devices in CMOS and BiCMOS technologies

Bipolar junction transistors with an air gap in the shallow trench isolation

Semiconductor structure with airgap

Planar cavity MEMS and related structures, methods of manufacture and design structures

Planar cavity MEMS and related structures, methods of manufacture and design structures

Planar cavity MEMS and related structures, methods of manufacture and design structures

AUTOMATED SHORT LENGHT WIRE SHAPE STRAPPING AND METHODS OF FABRICATING THE SAME

Method of manufacture MEMS switches with reduced voltage

Method of manufacturing MEMS switches with reduced voltage

Method of manufacturing MEMS switches with reduced switching voltage

Method of manufacturing MEMS switches with reduced switching volume

Micro-electro-mechanical system (MEMS) structures and design structures

Dielectric cover for a through silicon via

INDUCTOR STRUCTURE HAVING EMBEDDED AIRGAP

Lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a below source isolation region and a method of forming the LDMOSFET

Switchable filters and design structures

Micro-electro-mechanical system (MEMS) structures and design structures

Semiconductor structures having low resistance paths throughout a wafer

Semiconductor structures having low resistance paths throughout a wafer

Semiconductor structures having low resistance paths throughout a wafer

Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure

Silicon waveguide on bulk silicon substrate and methods of forming

Wafer frontside-backside through silicon via

Semiconductor structures having low resistance paths throughout a wafer

Switchable filters and design structures

Semiconductor structures provided within a cavity and related design structures

TSV WITH END CAP, METHOD AND 3D INTEGRATED CIRCUIT

Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure

Tunable filter structures and design structures

Backside integration of RF filters for RF front end modules and design structure

Altering capacitance of MIM capacitor having reactive layer therein

MEMS switches with reduced switching voltage and methods of manufacture

Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure

Heterojunction bipolar transistors with an airgap between the extrinsic base and collector

Handle wafer

Automated residual material detection

Method of eliminating poor reveal of through silicon vias