Jericho, Vermont
United States
172
2025-03-20
The entities that hold a legal rights for patent applications filed by inventor Hook Terence B.:
Terence B. Hook from Jericho, US has applied for patents for these inventions. The list has both pending applications and granted patents:
PROTECTION DIODE MATRIX FOR ANTENNA PROTECTION
#2 | 2023-09-21STABLE WORK FUNCTION FOR NARROW-PITCH DEVICES
#3 | 2022-10-06NANOSHEET FIELD EFFECT TRANSISTORS WITH PARTIAL INSIDE SPACERS
#4 | 2022-05-05Long channel and short channel vertical FET co-integration for vertical FET VTFET
#5 | 2021-09-09Performance-screen ring oscillator with switchable features
#6 | 2021-05-20Fully depleted SOI transistor with a buried ferroelectric layer in back-gate
#7 | 2020-08-13Checking wafer-level integrated designs for rule compliance
#8 | 2020-05-28Semiconductor device and method of forming the semiconductor device
#9 | 2020-05-21Vertical transistor contact for cross-coupling in a memory cell
#10 | 2020-05-14Integration of electrostatic discharge protection into vertical fin technology
#11 | 2020-05-07Vertical field-effect transistor with a bottom contact that exhibits low electrical resistance
#12 | 2020-04-30Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices
#13 | 2020-04-30Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices
#14 | 2020-04-30Stack viabar structures
#15 | 2020-04-23Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devices
#16 | 2020-04-02Vertical transistor contact for a memory cell with increased density
#17 | 2020-03-31Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices
#18 | 2020-03-26Nanosheet field effect transistors with partial inside spacers
#19 | 2020-02-27Integration of input/output device in vertical field-effect transistor technology
#20 | 2020-02-27Contact-first field-effect transistors
#21 | 2020-02-27Fully depleted SOI transistor with a buried ferroelectric layer in back-gate
#22 | 2020-02-27Integrating a junction field effect transistor into a vertical field effect transistor
#23 | 2020-01-16Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device
#24 | 2020-01-16Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device
#25 | 2020-01-09Integration of input/output device in vertical field-effect transistor technology
#26 | 2020-01-02Vertical transistor contact for cross-coupling in a memory cell
#27 | 2020-01-02Vertical transistor contact for a memory cell with increased density
#28 | 2019-12-10Integrating a junction field effect transistor into a vertical field effect transistor
#29 | 2019-12-05Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device
#30 | 2019-10-24Logic gate designs for 3D monolithic direct stacked VTFET
#31 | 2019-08-29Fully-depleted CMOS transistors with u-shaped channel
#32 | 2019-08-22Checking wafer-level integrated designs for rule compliance
#33 | 2019-08-15MULTIPLE-THRESHOLD NANOSHEET TRANSISTORS
#34 | 2019-07-25Logic gate designs for 3D monolithic direct stacked VTFET
#35 | 2019-06-27Integration of input/output device in vertical field-effect transistor technology
#36 | 2019-05-07Stacked vertical transistor device for three-dimensional monolithic integration
#37 | 2019-05-02Electrostatic discharge protection using vertical fin CMOS technology
#38 | 2019-01-31FinFETs with various fin height
#39 | 2018-12-13Lateral non-volatile storage cell
#40 | 2018-11-06Vertical field effect transistor with metallic bottom region
#41 | 2018-10-23Lateral non-volatile storage cell
#42 | 2018-09-06Nanosheet MOSFET with partial release and source/drain epitaxy
#43 | 2018-08-30Independent gate FinFET with backside gate contact
#44 | 2018-08-30Independent gate FinFET with backside gate contact
#45 | 2018-08-23Fully-depleted silicon-on-insulator transistors
#46 | 2018-08-09Semiconductor device with low band-to-band tunneling
#47 | 2018-08-09Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer
#48 | 2018-08-02Nanosheet field effect transistors with partial inside spacers
#49 | 2018-08-02Nanosheet field effect transistors with partial inside spacers
#50 | 2018-07-19Method and structures for personalizing lithography
#51 | 2018-07-12FinFETs with various fin height
#52 | 2018-07-05Checking wafer-level integrated designs for antenna rule compliance
#53 | 2018-06-28Structure and method for fully depleted silicon on insulator structure for threshold voltage modification
#54 | 2018-05-03Semiconductor device and method of forming the semiconductor device
#55 | 2018-04-26Multiple-threshold nanosheet transistors
#56 | 2018-04-19Semiconductor device and method of forming the semiconductor device
#57 | 2018-04-12Mirror contact capacitor
#58 | 2018-04-05Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer
#59 | 2018-03-29Fully-depleted CMOS transistors with U-shaped channel
#60 | 2018-03-29Bipolar transistor compatible with vertical FET fabrication
#61 | 2018-03-29Bipolar transistor compatible with vertical FET fabrication
#62 | 2018-03-22Bulk to silicon on insulator device
#63 | 2018-03-22Stable work function for narrow-pitch devices
#64 | 2018-03-22Independently driving built-in self test circuitry over a range of operating conditions
#65 | 2018-02-01Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process
#66 | 2018-01-18Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process
#67 | 2018-01-04Mirrored contact CMOS with self-aligned source, drain, and back-gate
#68 | 2018-01-04Long channel and short channel vertical FET co-integration for vertical FET VTFET
#69 | 2018-01-02Bipolar transistor compatible with vertical FET fabrication
#70 | 2017-12-28Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process
#71 | 2017-12-28Mirror contact capacitor
#72 | 2017-12-21Structures and methods for long-channel devices in nanosheet technology
#73 | 2017-12-21Semiconductor device with different fin pitches
#74 | 2017-11-09Bottom source/drain silicidation for vertical field-effect transistor (FET)
#75 | 2017-11-02Semiconductor device with different fin pitches
#76 | 2017-11-02BOTTOM SOURCE/DRAIN SILICIDATION FOR VERTICAL FIELD-EFFECT TRANSISTOR (FET)
#77 | 2017-10-12Bulk to silicon on insulator device
#78 | 2017-10-12Bulk to silicon on insulator device
#79 | 2017-10-12Bulk to silicon on insulator device
#80 | 2017-10-12Bulk to silicon on insulator device
#81 | 2017-10-05Extra gate device for nanosheet
#82 | 2017-09-28Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer
#83 | 2017-09-28Checking wafer-level integrated designs for rule compliance
#84 | 2017-09-21Checking wafer-level integrated designs for antenna rule compliance
#85 | 2017-09-12Multiple back gate transistor
#86 | 2017-07-18Interlayer via
#87 | 2017-07-06Extra gate device for nanosheet
#88 | 2017-07-06Extra gate device for nanosheet
#89 | 2017-07-06Extra gate device for nanosheet
#90 | 2017-07-06Bottom source/drain silicidation for vertical field-effect transistor (FET)
#91 | 2017-06-22Structure and method for fully depleted silicon on insulator structure for threshold voltage modification
#92 | 2017-06-15Structure and method to minimize junction capacitance in NANO sheets
#93 | 2017-05-25Stable work function for narrow-pitch devices
#94 | 2017-05-25STABLE WORK FUNCTION FOR NARROW-PITCH DEVICES
#95 | 2017-05-16Semiconductor device with different fin pitches
#96 | 2017-05-11Semiconductor device with low band-to-band tunneling
#97 | 2017-05-11Semiconductor device with low band-to-band tunneling
#98 | 2017-04-13Devices with multiple threshold voltages formed on a single wafer using strain in the high-K layer
#99 | 2017-04-13Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer
#100 | 2017-04-13Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer
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