Gregory S. Snider

Configurable molecular switch array

Mixed-scale electronic interface

Nanoscale shift register and signal demultiplexing using microscale/nanoscale shift registers

Nanowire Crossbar Implementations of logic Gates using configurable, tunneling resistor junctions

Processor and programmable logic computing arrangement

Computational nodes and computational-node networks that include dynamical-nanodevice connections

Nanoscale electronic latch

FPGA architecture at conventional and submicron scales

Three-dimensional crossbar array systems and methods for writing information to and reading information stored in three-dimensional crossbar array junctions

Methods and systems for implementing logic gates with spintronic devices located at nanowire crossbar junctions of crossbar arrays

Method for fabricating nanoscale features

Mixed-scale electronic interface

Tunneling-resistor-junction-based microscale/nanoscale demultiplexer arrays

FPGA architecture at conventional and submicron scales

Mixed-scale electronic interface

Compute clusters employing photonic interconnections for transmitting optical signals between compute cluster nodes

Partitionable data fabric and computing arrangement

Nanoscale latch-array processing engines

Nanowire crossbar implementations of logic gates using configurable, tunneling resistor junctions

Nanoscale shift register and signal demultiplexing using microscale/nanoscale shift registers

Reduction of storage elements in synthesized synchronous circuits

Enhanced nanowire-crossbar latch array

Interconnectable nanoscale computational stages

Factored nanoscale multiplexer/demultiplexer circuit for interfacing nanowires with microscale and sub-microscale electronic devices

Antisymmetric nanowire crossbars

Method for reducing the size and nanowire length used in nanowire crossbars without reducing the number of nanowire junctions

Method for allocating resources in heterogeneous nanowire crossbars having defective nanowire junctions

Nanoscale latches and impedance-encoded logic for use in nanoscale state machines, nanoscale pipelines, and in other nanoscale electronic circuits

Method and apparatus for compiling source code to configure hardware

Pipelined digital circuit for determining the conformational energy of a folded protein

Molecular wire content addressable memory

Efficient pipelining of synthesized synchronous circuits