Jeffrey S. Brown

On demand circuit function execution employing optical sensing

Structure for a voltage detection circuit in an integrated circuit and method of generating a trigger flag signal

Semiconductor structure and system for fabricating an integrated circuit chip

Voltage detection circuit in an integrated circuit and method of generating a trigger flag signal

Voltage detection circuit and circuit for generating a trigger flag signal

Method and structure to process thick and thin fins and variable fin to fin spacing

METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING

METHOD OF FORMING HIGH VOLTAGE N-LDMOS TRANSISTORS HAVING SHALLOW TRENCH ISOLATION REGION WITH DRAIN EXTENSIONS

Method and structure to process thick and thin fins and variable fin to fin spacing

On demand circuit function execution employing optical sensing

Concurrent Fin-FET and thick-body device fabrication

Concurrent fin-fet and thick body device fabrication

Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure

E-Fuse and anti-E-Fuse device structures and methods

Integrated antifuse structure for FINFET and CMOS devices

Zero threshold voltage pFET and method of making same

MOSFET with decoupled halo before extension

Method for scalable, low-cost polysilicon capacitor in a planar DRAM

DRAM cell with enhanced SER immunity

Method of forming high voltage N-LDMOS transistors having shallow trench isolation region with drain extensions

Selective silicide blocking

High voltage N-LDMOS transistors having shallow trench isolation region

DRAM cell with enhanced SER immunity