Inventor profile of:

Peter Javorka

City:

Dresden

Country:

Germany

Published Applications:

12

Last publication date:

2025-07-17

Top Assignees for applications by Peter Javorka

The entities that hold a legal rights for patent applications filed by inventor Javorka Peter:

Recent patent applications by Javorka Peter

Peter Javorka from Dresden, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-07-17
US20250234585A1
Electricity

EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR (EDMOS) FIELD EFFECT TRANSISTOR (FET) WITH DUAL THICKNESS SEMICONDUCTOR MATERIAL

#2 | 2025-06-10
US18675367
Electricity

Structures for a field-effect transistor that include a spacer structure

#3 | 2022-05-05
US20220140131A1
Electricity

Transistor with phase transition material region between channel region and each source/drain region

#4 | 2010-06-24
US20100155850A1
Electricity

Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions

#5 | 2009-09-24
US20090236667A1
Electricity

Semiconductor device comprising isolation trenches inducing different types of strain

#6 | 2009-01-01
US20090001479A1
Electricity

TRANSISTOR HAVING REDUCED GATE RESISTANCE AND ENHANCED STRESS TRANSFER EFFICIENCY AND METHOD OF FORMING THE SAME

#7 | 2008-04-03
US20080079085A1
Electricity

Method of making a semiconductor device comprising isolation trenches inducing different types of strain

#8 | 2007-11-01
US20070254444A1
Electricity

Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regions

#9 | 2007-10-04
US20070228482A1
Electricity

Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions

#10 | 2007-08-30
US20070202653A1
Electricity

Technique for forming a strained transistor by a late amorphization and disposable spacers

#11 | 2007-05-31
US20070123010A1
Electricity

TECHNIQUE FOR REDUCING CRYSTAL DEFECTS IN STRAINED TRANSISTORS BY TILTED PREAMORPHIZATION

#12 | 2007-05-31
US20070122966A1
Electricity

Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors

InventorID:

3803157 ⎘