Inventor profile of:

Emre ÖZER

City:

Cambridge

Country:

United Kingdom

Published Applications:

22

Last publication date:

2023-04-06

Top Assignees for applications by Emre ÖZER

The entities that hold a legal rights for patent applications filed by inventor ÖZER Emre:

Recent patent applications by ÖZER Emre

Emre ÖZER from Cambridge, GB has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2023-04-06
US20230108006A1
Human necessities

PACKAGING FOR A PHARMACEUTICAL PRODUCT

#2 | 2022-07-28
US20220236124A1
Physics

Circuitry fabricated on a flexible substrate

#3 | 2022-07-21
US20220230033A1
Physics

Energy efficient smart label with an electrically destructible fuse

#4 | 2022-05-19
US20220156531A1
Physics

Feature dataset classification

#5 | 2021-09-09
US20210279124A1
Physics

Memory scanning operation in response to common mode fault signal

#6 | 2017-03-16
US20170075760A1
Physics

Error protection

#7 | 2015-06-04
US20150154045A1
Physics

CONTENTION MANAGEMENT FOR A HARDWARE TRANSACTIONAL MEMORY

#8 | 2013-10-24
US20130283115A1
Electricity

Data processing apparatus using implicit data storage data storage and method of implicit data storage

#9 | 2013-08-08
US20130205080A1
Physics

Apparatus and method for controlling refreshing of data in a DRAM

#10 | 2012-10-04
US20120254698A1
Physics

Memory scrubbing

#11 | 2012-05-24
US20120131313A1
Physics

Error recovery following speculative execution with an instruction processing pipeline

#12 | 2010-03-11
US20100064109A1
Physics

Managing the storage of high-priority storage items in storage units in multi-core and multi-threaded systems using history storage and control circuitry

#13 | 2009-09-03
US20090222625A1
Physics

Cache miss detection in a data processing apparatus

#14 | 2009-04-23
US20090106616A1
Physics

Integrated circuit using speculative execution

#15 | 2008-11-27
US20080295105A1
Physics

Data processing apparatus and method for managing multiple program threads executed by processing circuitry

#16 | 2008-11-13
US20080282067A1
Physics

Issue policy control within a multi-threaded in-order superscalar processor

#17 | 2008-10-30
US20080270758A1
Physics

Multiple thread instruction fetch from different cache levels

#18 | 2008-10-30
US20080270749A1
Physics

Instruction issue control within a multi-threaded in-order superscalar processor

#19 | 2008-10-23
US20080263341A1
Physics

Data processing apparatus and method for updating prediction data based on an operation's priority level

#20 | 2008-10-09
US20080250271A1
Physics

Error recovery following speculative execution with an instruction processing pipeline

#21 | 2008-09-18
US20080229052A1
Physics

Data processing apparatus and method for implementing a replacement scheme for entries of a storage unit

#22 | 2008-08-28
US20080209133A1
Physics

Managing cache coherency in a data processing apparatus

InventorID:

381036