Austin, Texas
United States
264
2024-06-27
The entities that hold a legal rights for patent applications filed by inventor Guthrie Guy L.:
Guy L. Guthrie from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Centralized distribution of multicast requests in a data processing system
#2 | 2023-09-05Concurrent processing of translation entry invalidation requests in a processor core
#3 | 2023-07-13Prefetch unit filter for microprocessor
#4 | 2023-07-04Gathering translation entry invalidation requests in a data processing system
#5 | 2023-03-16Using idle caches as a backing store for boot code
#6 | 2023-03-02Prioritization of threads in a simultaneous multithreading processor core
#7 | 2023-02-23Broadcast scope selection in a data processing system utilizing a memory topology data structure
#8 | 2023-02-09Targeting of lateral castouts in a data processing system
#9 | 2023-02-09Speculative delivery of data from a lower level of a memory hierarchy in a data processing system
#10 | 2023-02-09Distribution of injected data among caches of a data processing system
#11 | 2023-02-02Memory migration within a multi-host data processing environment
#12 | 2022-12-27Marking in-flight requests affected by translation entry invalidation in a data processing system
#13 | 2022-12-22Variable protection window extension for a target address of a store-conditional request
#14 | 2022-12-22Adjusting store gather window duration in a data processing system supporting simultaneous multithreading
#15 | 2022-05-19Accelerated processing of streams of load-reserve requests
#16 | 2022-02-03Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations
#17 | 2021-11-04Initiating interconnect operation without waiting on lower level cache directory lookup
#18 | 2021-07-15Completion logic performing early commitment of a store-conditional access based on a flag
#19 | 2021-06-17Cache snooping mode extending coherence protection for certain requests
#20 | 2021-06-17Cache snooping mode extending coherence protection for certain requests
#21 | 2021-04-01Cache-inhibited write operations
#22 | 2020-12-31Ordering execution of an interrupt handler
#23 | 2020-11-12Low latency management of processor core wait state
#24 | 2020-11-10Ordering execution of an interrupt handler
#25 | 2020-08-20Atomic memory operation having selectable location of performance
#26 | 2020-06-25Selectively updating a coherence state in response to a storage update
#27 | 2020-06-25Selectively updating a coherence state in response to a storage update
#28 | 2020-06-25Selectively updating a coherence state in response to a storage update
#29 | 2020-06-11Processing a sequence of translation entry invalidation requests with regard to draining a processor core
#30 | 2020-06-11Translation entry invalidation in a multithreaded data processing system
#31 | 2020-06-11Synchronized access to data in shared memory by protecting the load target address of a fronting load
#32 | 2020-06-11Zeroing a memory block without processor caching
#33 | 2020-06-04Selectively preventing pre-coherence point reads in a cache hierarchy to reduce barrier overhead
#34 | 2020-05-14Data flush of a persistent memory cache or buffer
#35 | 2020-05-14Synchronized access to data in shared memory by resolving conflicting accesses by co-located hardware threads
#36 | 2020-04-30Synchronized access to data in shared memory by protecting the load target address of a load-reserve instruction
#37 | 2020-04-09Information handling system with immediate scheduling of load operations
#38 | 2020-01-30Synchronized access to shared memory by extending protection for a store target address of a store-conditional request
#39 | 2020-01-30Dynamic transaction throttling in a data processing system supporting transactional memory
#40 | 2020-01-30SYNCHRONIZED ACCESS TO DATA IN SHARED MEMORY BY PROTECTING THE LOAD TARGET ADDRESS OF A FRONTING LOAD
#41 | 2019-12-05Managing efficient selection of a particular processor thread for handling an interrupt
#42 | 2019-08-29Adaptively enabling and disabling snooping bus commands
#43 | 2019-07-18Remote node broadcast of requests in a multinode data processing system
#44 | 2019-06-20Coherence protocol providing speculative coherence response to directory probe
#45 | 2019-05-30Accelerator memory coherency with single state machine
#46 | 2019-05-09Split transaction coherency protocol in a data processing system
#47 | 2019-04-25Managing efficient selection of a particular processor thread for handling an interrupt
#48 | 2019-02-28Ensuring forward progress for nested translations in a memory management unit
#49 | 2019-02-28Ensuring forward progress for nested translations in a memory management unit
#50 | 2019-02-28Reducing translation latency within a memory management unit using external caching structures
#51 | 2019-02-28Reducing translation latency within a memory management unit using external caching structures
#52 | 2019-02-07Techniques for command arbitation in symmetric multiprocessor systems
#53 | 2019-02-07Victim cache line selection
#54 | 2019-02-07Master requesting missing segments of a cache line for which the master has coherence ownership
#55 | 2019-02-07Techniques for managing a hang condition in a data processing system with shared memory
#56 | 2018-12-27Efficient enforcement of barriers with respect to memory move sequences
#57 | 2018-12-06Temporarily favoring selection of store requests from one of multiple store queues for issuance to a bank of a banked cache
#58 | 2018-12-06Banked cache temporarily favoring selection of store requests from one of multiple store queues
#59 | 2018-12-06Multicopy atomic store operation in a data processing system
#60 | 2018-12-06Multicopy atomic store operation in a data processing system
#61 | 2018-11-29Prefetch performance
#62 | 2018-11-29Prefetch performance
#63 | 2018-11-15Implementing barriers to efficiently support cumulativity in a weakly ordered memory system
#64 | 2018-11-08Speculatively performing memory move requests with respect to a barrier
#65 | 2018-06-14Simulation employing level-dependent multitype events
#66 | 2018-02-22Memory move supporting speculative acquisition of source and destination data granules including copy-type and paste-type instructions
#67 | 2018-02-22Adaptively enabling and disabling snooping bus commands
#68 | 2018-02-22Memory move instruction sequence including a stream of copy-type and paste-type instructions
#69 | 2018-02-22Speculatively performing memory move requests with respect to a barrier
#70 | 2018-02-22Memory move instruction sequence enabling software control
#71 | 2018-02-22Migration of memory move instruction sequences between hardware threads
#72 | 2018-02-22Efficient enforcement of barriers with respect to memory move sequences
#73 | 2018-02-22Memory access in a data processing system utilizing copy and paste instructions
#74 | 2018-02-22Memory move instruction sequence targeting a memory-mapped device
#75 | 2017-11-23Accessing partial cachelines in a data cache
#76 | 2017-11-02Implementing barriers to efficiently support cumulativity in a weakly-ordered memory system
#77 | 2017-11-02Implementing barriers to efficiently support cumulativity in a weakly-ordered memory system
#78 | 2017-10-12Early freeing of a snoop machine of a data processing system prior to completion of snoop processing for an interconnect operation
#79 | 2017-10-12Decreasing the data handoff interval for a reserved cache line based on an early indication of a systemwide coherence response
#80 | 2017-10-12Decreasing the data handoff interval in a multiprocessor data processing system based on an early indication of a systemwide coherence response
#81 | 2017-10-10Translation entry invalidation in a multithreaded data processing system
#82 | 2017-09-26Translation entry invalidation in a multithreaded data processing system
#83 | 2017-09-05Hybrid replacement policy in a multilevel cache memory hierarchy
#84 | 2017-08-08Counter-based victim selection in a cache memory
#85 | 2017-08-08Counter-based victim selection in a cache memory
#86 | 2017-06-22Translation entry invalidation in a multithreaded data processing system
#87 | 2017-06-22Translation entry invalidation in a multithreaded data processing system
#88 | 2017-06-22Translation entry invalidation in a multithreaded data processing system
#89 | 2017-06-22Translation entry invalidation in a multithreaded data processing system
#90 | 2017-06-22Translation entry invalidation in a multithreaded data processing system
#91 | 2017-05-30Injection of at least a partial cache line in a private multilevel cache hierarchy
#92 | 2017-03-02Expedited servicing of store operations in a data processing system
#93 | 2017-03-02Expedited servicing of store operations in a data processing system
#94 | 2017-03-02Expedited servicing of store operations in a data processing system
#95 | 2017-03-02Expedited servicing of store operations in a data processing system
#96 | 2017-03-02Expedited servicing of store operations in a data processing system
#97 | 2017-03-02Expedited servicing of store operations in a data processing system
#98 | 2017-03-02Expedited servicing of store operations in a data processing system
#99 | 2017-03-02Expedited servicing of store operations in a data processing system
#100 | 2017-02-21Translation entry invalidation in a multithreaded data processing system
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