Inventor profile of:

Martin Eckert

City:

Moetzingen

Country:

Germany

Published Applications:

34

Last publication date:

2021-07-15

Top Assignees for applications by Martin Eckert

The entities that hold a legal rights for patent applications filed by inventor Eckert Martin:

Recent patent applications by Eckert Martin

Martin Eckert from Moetzingen, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2021-07-15
US20210215738A1
Physics

Device for positioning a semiconductor die in a wafer prober

#2 | 2021-04-29
US20210123969A1
Physics

Stressing integrated circuits using a radiation source

#3 | 2021-03-04
US20210066183A1
Electricity

Integrated circuit with optical tunnel

#4 | 2019-12-26
US20190391179A1
Physics

Probe card alignment

#5 | 2019-07-04
US20190206492A1
Physics

Content addressable memory with match hit quality indication

#6 | 2019-07-04
US20190204138A1
Physics

Adjustable load transmitter

#7 | 2019-05-30
US20190163596A1
Physics

Functional testing of high-speed serial links

#8 | 2019-01-17
US20190018044A1
Physics

Probe card alignment

#9 | 2019-01-17
US20190018043A1
Physics

Probe card alignment

#10 | 2019-01-17
US20190017861A1
Physics

Adjustable load transmitter

#11 | 2018-12-04
US15795313
Physics

Adjustable load transmitter

#12 | 2018-09-25
US15858324
Physics

Adjustable load transmitter

#13 | 2018-09-25
US15858177
Physics

Probe card alignment

#14 | 2018-07-19
US20180204618A1
Physics

Content addressable memory with match hit quality indication

#15 | 2018-04-19
US20180107771A1
Physics

Layout effect characterization for integrated circuits

#16 | 2018-02-27
US15594782
Physics

Layout effect characterization for integrated circuits

#17 | 2018-02-13
US15406866
Physics

Content addressable memory with match hit quality indication

#18 | 2017-08-22
US15292422
Physics

Layout effect characterization for integrated circuits

#19 | 2017-06-08
US20170162534A1
Electricity

Chip attach frame

#20 | 2017-04-11
US15150822
Physics

Determining categories for memory fail conditions

#21 | 2017-03-30
US20170092377A1
Physics

RAM at speed flexible timing and setup control

#22 | 2017-03-30
US20170092341A1
Physics

RAM at speed flexible timing and setup control

#23 | 2016-10-06
US20160293497A1
Electricity

Soldering three dimensional integrated circuits

#24 | 2016-07-26
US14948743
Physics

Determining categories for memory fail conditions

#25 | 2016-04-07
US20160097807A1
Physics

Method for electrical testing of a 3-D chip stack

#26 | 2015-07-16
US20150201537A9
Electricity

Chip attach frame

#27 | 2015-03-05
US20150059166A1
Electricity

CHIP ATTACH FRAME

#28 | 2014-10-23
US20140316725A1
Physics

Power noise histogram of a computer system

#29 | 2014-10-09
US20140300382A1
Physics

System for electrical testing and manufacturing of a 3-D chip stack and method

#30 | 2013-12-26
US20130343200A1
Electricity

Network power fault detection

#31 | 2013-08-15
US20130207250A1
Electricity

Chip attach frame

#32 | 2012-05-17
US20120123724A1
Electricity

Detecting an unstable input to an IC

#33 | 2012-01-19
US20120013356A1
Physics

Method and system for performing self-tests in an electronic system

#34 | 2010-06-03
US20100135570A1
Physics

Test fail analysis on VLSI chips

InventorID:

384924 ⎘