Altera Corporation

Mapping network applications to a hybrid programmable many-core device

Hybrid programmable many-core device with on-chip interconnect

Apparatus for improved communication and associated methods

Circuits and methods for DQS autogating

APPARATUS FOR ELECTRONIC ASSEMBLY WITH IMPROVED INTERCONNECT AND ASSOCIATED METHODS

SUB-RATE MAPPING FOR LOWEST-ORDER OPTICAL DATA UNIT

Heat pipe in overmolded flip chip package

Heat spreading in molded semiconductor packages

Parallel decomposition of Reed Solomon umbrella codes

Techniques for alignment of parallel signals

Bypassable clocked storage circuitry for dynamic voltage-frequency scaling

Integrated circuit package with active interposer

Methods and apparatus for aligning clock signals on an integrated circuit

METAL-PROGRAMMABLE INTEGRATED CIRCUITS

Partitioning designs to facilitate certification

3D built-in self-test scheme for 3D assembly defect detection

Integrated circuit device with stitched interposer

Apparatus and methods for equalizer adaptation

Memory elements with stacked pull-up devices

ANTENNA DIODE CIRCUITRY AND METHOD OF MANUFACTURE

METHOD AND APPARATUS FOR TRANSLATING GRAPHICAL SYMBOLS INTO QUERY KEYWORDS

Memory interface circuitry with improved timing margins

Methods for testing network circuitry

Apparatus and methods for adaptive receiver delay equalization

Techniques and circuitry for configuring and calibrating an integrated circuit

Methods and apparatus for building bus interconnection networks using programmable interconnection resources

3D memory based address generator for computationally efficient architectures

Look up table (LUT) structure supporting exclusive OR (XOR) circuitry configured to allow for generation of a result using quaternary adders

Adaptable datapath for a digital processing system

PLD architecture for flexible placement of IP function blocks

Apparatus and methods for time-multiplex field-programmable gate arrays