San Jose, California
United States
24
2013-05-14
The entities that hold a legal rights for patent applications filed by inventor Starr Gregory:
Gregory Starr from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Configurable clock network for programmable logic device
#2 | 2013-01-29Programmable logic device with specialized functional block
#3 | 2012-08-28Configurable clock network for programmable logic device
#4 | 2011-12-06Configurable clock network for programmable logic device
#5 | 2010-12-28Configurable clock network for programmable logic device
#6 | 2010-04-13Programmable logic device with specialized functional block
#7 | 2010-01-12Configurable clock network for programmable logic device
#8 | 2009-02-12Dynamic phase alignment methods and apparatus
#9 | 2008-03-18Devices and methods with programmable logic and digital signal processing regions
#10 | 2007-10-23Configurable clock network for programmable logic device
#11 | 2007-03-20Differential output buffer with super size
#12 | 2007-02-20Apparatus and method for decreasing the lock time of a lock loop circuit
#13 | 2006-10-10Devices and methods with programmable logic and digital signal processing regions
#14 | 2006-07-20Programmable phase-locked loop circuitry for programmable logic device
#15 | 2006-07-11Configurable clock network for programmable logic device
#16 | 2006-05-18Programmable logic device including multipliers and configurations thereof to reduce resource utilization
#17 | 2005-11-24Dynamic phase alignment methods and apparatus
#18 | 2005-10-25Data latch with low-power bypass mode
#19 | 2005-09-22Programmable phase-locked loop circuitry for programmable logic device
#20 | 2005-08-30Specialized programmable logic region with low-power mode
#21 | 2005-08-25Multiplier-accumulator block mode splitting
#22 | 2005-04-21Programmable phase-locked loop circuitry for programmable logic device
#23 | 2005-03-10Dual-gain loop circuitry for programmable logic device
#24 | 2005-02-17Programmable logic device including multipliers and configurations thereof to reduce resource utilization
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