James Stephen Fields, JR.

L2 cache controller with slice directory and unified cache structure

Providing low-level hardware access to in-band and out-of-band firmware

Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing

Recovering from errors in a data processing system

Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor

Apparatus for operating cache-inhibited memory mapped commands to access registers

Efficient coherency communication utilizing an IG coherency state

Victim cache using direct intervention

Data processing system and method for efficient communication utilizing an Tn and Ten coherency states

Efficient storage of metadata in a system memory

Data processing system and method for efficient coherency communication utilizing coherency domain indicators

Method and apparatus for automatically identifying multiple combinations of operational and non-operational components on integrated circuit chips with a single part number

Method and apparatus for automatic recovery from a failed node concurrent maintenance operation

Victim cache using direct intervention

Method and apparatus for multiplexing commands in a symmetric multiprocessing system interchip link

System and method for recovering from errors in a data processing system

Dynamic power management via DIMM read operation limiter

Method to operate cache-inhibited memory mapped commands to access registers

Data processing system and method for efficient storage of metadata in a system memory

Data processing system and method for efficient communication utilizing an Ig coherency state

Data processing system and method for efficient coherency communication utilizing coherency domain indicators

Data processing system and method for efficient communication utilizing an Tn and Ten coherency states

Data processing system and method for efficient coherency communication utilizing coherency domains

Half-good mode for large L2 cache array topology with different latency domains

L2 cache controller with slice directory and unified cache structure

Method to preserve ordering of read and write operations in a DMA system by delaying read access

Method for providing low-level hardware access to in-band and out-of-band firmware

Method and apparatus for autonomic policy-based thermal management in a data processing system

Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor

Apparatus and method for accurately tuning the speed of an integrated circuit

Adaptive memory access speculation

Method, system, and program for transferring data directed to virtual memory addresses to a device memory

Method and system for handling multiple bit errors to enhance system reliability

Data processing system and method of communication that employ a request-and-forget protocol

Memory directory management in a multi-node computer system

Dynamic history based mechanism for the granting of exclusive data ownership in a non-uniform memory access (NUMA) computer system

Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes

Method, system and program product providing a configuration specification language that supports the definition of links between configuration constructs

Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response