Allen, Texas
United States
33
2011-04-14
The entities that hold a legal rights for patent applications filed by inventor Whetsel Lee D.:
Lee D. Whetsel from Allen, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Multiplexer selecting STP clock signal with tap control outputs
#2 | 2011-03-10Clock and mode signals controlling data communication in three states
#3 | 2009-03-05Parallel scan distributors and collectors and process of testing integrated circuits
#4 | 2008-07-22Circuitry with multiplexed dedicated and shared scan path cells
#5 | 2007-12-13Selecting between tap/scan with instructions and lock out signal
#6 | 2007-10-09Data retaining boundary scan cell
#7 | 2007-08-14Probeless testing of pad buffers on wafer
#8 | 2007-05-01IEEE 1149.1 tap instruction scan with augmented TLM scan mode
#9 | 2007-02-27Comparing on die response and expected response applied to outputs
#10 | 2006-12-26IC with separate scan paths and shift states
#11 | 2006-12-26Tap and test controller with separate enable inputs
#12 | 2006-10-31Means scanning scan path parts sequentially and capturing response simultaneously
#13 | 2006-10-10IC with scan distributor and scan collector circuitry
#14 | 2006-06-20IC with external register present lead connected to instruction register
#15 | 2006-06-06Selecting different 1149.1 TAP domains from update-IR state
#16 | 2006-03-23IC with TAP, STP and lock out controlled output buffer
#17 | 2006-02-21IC tap/scan test port access with tap lock circuitry
#18 | 2006-01-26First and second scan distributors, collectors, controllers, and multiplexers
#19 | 2006-01-17System with functional and selector circuits connected by mode lead
#20 | 2006-01-10Testing ICs with distributor, collector, and parallel scan paths
#21 | 2005-12-22Selecting groups of dies for wafer testing
#22 | 2005-12-13Hierarchical linking module connection to access ports of embedded cores
#23 | 2005-12-08Selecting between two TAP circuits with MODE/TCK and TCK/MODE signals
#24 | 2005-11-24Fault tolerant selection of die on wafer
#25 | 2005-11-08Quad state logic design methods, circuits, and systems
#26 | 2005-10-11Method and apparatus for die testing on wafer
#27 | 2005-09-15Response bits as stimulus in subdivided scan path delay test
#28 | 2005-09-13Plural circuit selection using role reversing control inputs
#29 | 2005-08-18Quad state memory with converter feedback, transmission, and clock circuitry
#30 | 2005-05-24IC with cache bit memory in series with scan segment
#31 | 2005-03-03Tap with separate scan cell in series with instruction register
#32 | 2005-03-03JTAG state machines with respective enable input and select input
#33 | 2005-01-06Means scanning scan path parts sequentially and capturing response simultaneously
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