Inventor profile of:

Lee D. Whetsel

City:

Allen, Texas

Country:

United States

Published Applications:

33

Last publication date:

2011-04-14

Top Assignees for applications by Lee D. Whetsel

The entities that hold a legal rights for patent applications filed by inventor Whetsel Lee D.:

Recent patent applications by Whetsel Lee D.

Lee D. Whetsel from Allen, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2011-04-14
US20110087939A1
Physics

Multiplexer selecting STP clock signal with tap control outputs

#2 | 2011-03-10
US20110058634A1
Physics

Clock and mode signals controlling data communication in three states

#3 | 2009-03-05
US20090063920A1
Physics

Parallel scan distributors and collectors and process of testing integrated circuits

#4 | 2008-07-22
US10814671
-

Circuitry with multiplexed dedicated and shared scan path cells

#5 | 2007-12-13
US20070288820A1
Physics

Selecting between tap/scan with instructions and lock out signal

#6 | 2007-10-09
US10609757
-

Data retaining boundary scan cell

#7 | 2007-08-14
US10806539
-

Probeless testing of pad buffers on wafer

#8 | 2007-05-01
US10772982
-

IEEE 1149.1 tap instruction scan with augmented TLM scan mode

#9 | 2007-02-27
US10806546
-

Comparing on die response and expected response applied to outputs

#10 | 2006-12-26
US10771768
-

IC with separate scan paths and shift states

#11 | 2006-12-26
US10114193
-

Tap and test controller with separate enable inputs

#12 | 2006-10-31
US10887370
-

Means scanning scan path parts sequentially and capturing response simultaneously

#13 | 2006-10-10
US10816073
-

IC with scan distributor and scan collector circuitry

#14 | 2006-06-20
US10705648
-

IC with external register present lead connected to instruction register

#15 | 2006-06-06
US9864509
-

Selecting different 1149.1 TAP domains from update-IR state

#16 | 2006-03-23
US20060064613A1
Physics

IC with TAP, STP and lock out controlled output buffer

#17 | 2006-02-21
US9845879
-

IC tap/scan test port access with tap lock circuitry

#18 | 2006-01-26
US20060017453A1
Physics

First and second scan distributors, collectors, controllers, and multiplexers

#19 | 2006-01-17
US9697941
-

System with functional and selector circuits connected by mode lead

#20 | 2006-01-10
US10695241
-

Testing ICs with distributor, collector, and parallel scan paths

#21 | 2005-12-22
US20050280434A1
Physics

Selecting groups of dies for wafer testing

#22 | 2005-12-13
US10172568
-

Hierarchical linking module connection to access ports of embedded cores

#23 | 2005-12-08
US20050270858A1
Physics

Selecting between two TAP circuits with MODE/TCK and TCK/MODE signals

#24 | 2005-11-24
US20050258857A1
Physics

Fault tolerant selection of die on wafer

#25 | 2005-11-08
US10618920
-

Quad state logic design methods, circuits, and systems

#26 | 2005-10-11
US10832919
-

Method and apparatus for die testing on wafer

#27 | 2005-09-15
US20050204228A1
Physics

Response bits as stimulus in subdivided scan path delay test

#28 | 2005-09-13
US10114572
-

Plural circuit selection using role reversing control inputs

#29 | 2005-08-18
US20050179462A1
Physics

Quad state memory with converter feedback, transmission, and clock circuitry

#30 | 2005-05-24
US9955542
-

IC with cache bit memory in series with scan segment

#31 | 2005-03-03
US20050050414A1
Physics

Tap with separate scan cell in series with instruction register

#32 | 2005-03-03
US20050050413A1
Physics

JTAG state machines with respective enable input and select input

#33 | 2005-01-06
US20050005219A1
Physics

Means scanning scan path parts sequentially and capturing response simultaneously

InventorID:

3897254 ⎘