Oleg Gluschenkov

Transistor and method of forming same

Transistor and method of forming same

Multiple nanosecond laser pulse anneal processes and resultant semiconductor structure

Silicon germanium heterojunction bipolar transistor structure and method

Dual pulse driven extreme ultraviolet (EUV) radiation source method

Asymmetric field effect transistor cap layer

Dual pulse driven extreme ultraviolet (EUV) radiation source utilizing a droplet comprising a metal core with dual concentric shells of buffer gas

Gas cluster reactor for anisotropic film growth

Silicon device on SI:C-OI and SGOI and method of manufacture

Silicon germanium heterojunction bipolar transistor structure and method

Structure and method for mobility enhanced MOSFETS with unalloyed silicide

Structure and method for mobility enhanced MOSFETs with unalloyed silicide

Silicon germanium heterojunction bipolar transistor structure and method

Inline low-damage automated failure analysis

Method for optimizing the routing of wafers/lots based on yield

Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof

Source/drain junction for high performance MOSFET formed by selective EPI process

METHOD OF FABRICATING GATE ELECTRODE FOR GATE OF MOSFET AND STRUCTURE THEREOF

ULTRAVIOLET UV PHOTO PROCESSING OR CURING OF THIN FILMS WITH SURFACE TREATMENT

INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONS

Method for fabricating a semiconductor structure

Structure for on-chip electromigration monitoring system

Silicon germanium heterojunction bipolar transistor structure and method

Semiconductor device and method of manufacture

Method for reducing overlap capacitance in field effect transistors

On-chip electromigration monitoring

Silicon germanium heterojunction bipolar transistor structure and method

Hybrid SOI/bulk semiconductor transistors

STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY

Structure and method for monitoring and characterizing pattern density dependence on thermal absorption in a semiconductor manufacturing process

Method for reducing overlap capacitance in field effect transistors

Structure and method for mobility enhanced MOSFETs with unalloyed silicide

SEMICONDUCTOR DEVICE STRUCTURE WITH ACTIVE REGIONS HAVING DIFFERENT SURFACE DIRECTIONS

Hybrid SOI-bulk semiconductor transistors

Method for forming a multi-gate device with high k dielectric for channel top surface

Stressed semiconductor device structures having granular semiconductor material

SINGLE IC-CHIP DESIGN ON WAFER WITH AN EMBEDDED SENSOR UTILIZING RF CAPABILITIES TO ENABLE REAL-TIME DATA TRANSMISSION

INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF

Field effect transistors with dielectric source drain halo regions and reduced miller capacitance

Method for manufacturing double gate finFET with asymmetric halo

Integrated circuit chip with FETs having mixed body thickness and method of manufacture thereof

Method for reducing overlap capacitance in field effect transistors

Epitaxy of Silicon-Carbon Substitutional Solid Solutions by Ultra-Fast Annealing of Amorphous Material

Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof

Dual stressed SOI substrates

Structure for reducing overlap capacitance in field effect transistors

On-chip electromigration monitoring system

Field effect transistors with dielectric source drain halo regions and reduced miller capacitance

Highly manufacturable SRAM cells in substrates with hybrid crystal orientation

MULTIPLE LOW AND HIGH K GATE OXIDES ON SINGLE GATE FOR LOWER MILLER CAPACITANCE AND IMPROVED DRIVE CURRENT

Structure for reducing overlap capacitance in field effect transistors

Anti-halo compensation

Method of forming an ultra-thin [[HfSiO]] metal silicate film for high performance CMOS applications and semiconductor structure formed in said method

SINGLE IC-CHIP DESIGN ON WAFER WITH AN EMBEDDED SENSOR UTILIZING RF CAPABILITIES TO ENABLE REAL-TIME DATA TRANSMISSION

Method of producing highly strained PECVD silicon nitride thin films at low temperature

STRUCTURE AND METHOD TO ENHANCE STRESS IN A CHANNEL OF CMOS DEVICES USING A THIN GATE

Method of fabricating a field effect transistor having improved junctions

CMOS transistor structure including film having reduced stress by exposure to atomic oxygen

Dual stressed SOI substrates

Nanocircuit and self-correcting etching method for fabricating same

Lowered Source/Drain Transistors

Oxidation method for altering a film structure

Self-aligned low-k gate cap

Gate electrode forming methods using conductive hard mask

Semiconductor device structure with active regions having different surface directions and methods

Multi-gate device with high k dielectric for channel top surface

Temperature stable metal nitride gate electrode

Nitride and polysilicon interface with titanium layer

Structure and method to improve channel mobility by gate electrode stress modification

Temperature stable metal nitride gate electrode

Logic circuits having linear and cellular gate transistors

MOSFET structure with high mechanical stress in the channel

Structure and method to improve channel mobility by gate electrode stress modification

Method for manufacturing tungsten/polysilicon word line structure in vertical DRAM

Method of fabricating mobility enhanced CMOS devices

Hybrid SOI/bulk semiconductor transistors

Method for forming a uniform distribution of nitrogen in silicon oxynitride gate dielectric

High performance FET with laterally thin extension

Gate metal recess for oxidation protection and parasitic capacitance reduction

Forming gate oxides having multiple thicknesses

Stressed semiconductor device structures having granular semiconductor material

Trench isolation employing a doped oxide trench fill

Oxidation method for altering a film structure and CMOS transistor structure formed therewith

Structure and method to improve channel mobility by gate electrode stress modification

High performance FET with laterally thin extension

Nanocircuit and self-correcting etching method for fabricating same

Method of fabricating a buried collar