Milpitas, California
United States
22
2015-12-01
The entities that hold a legal rights for patent applications filed by inventor Wang Chi-Lie:
Chi-Lie Wang from Milpitas, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Method and apparatus for congestion and fault management with time-to-live
#2 | 2014-12-02Method and apparatus for congestion and fault management with time-to-live
#3 | 2014-09-30Method and apparatus for unified final buffer with pointer-based and page-based scheme for traffic optimization
#4 | 2013-10-29Method and apparatus to optimize class of service under multiple VCs with mixed reliable transfer and continuous transfer modes
#5 | 2012-12-04Method and apparatus for dynamic traffic management with packet classification
#6 | 2012-11-27Method and apparatus for programmable buffer with dynamic allocation to optimize system throughput with deadlock avoidance on switches
#7 | 2012-08-28Method and apparatus for adaptive buffer management for traffic optimization on switches
#8 | 2012-08-07Method and apparatus for selective packet discard
#9 | 2009-09-10Power Management On sRIO Endpoint
#10 | 2009-09-10Serial buffer to support request packets with out of order response packets
#11 | 2009-09-10Protocol translation in a serial buffer
#12 | 2009-09-10Serial Buffer To Support Reliable Connection Between Rapid I/O End-Point And FPGA Lite-Weight Protocols
#13 | 2009-09-10Method to support lossless real time data sampling and processing on rapid I/O end-point
#14 | 2009-09-10Method to support flexible data transport on serial protocols
#15 | 2009-04-02Serial buffer supporting virtual queue to physical memory mapping
#16 | 2009-04-02Adaptive interrupt on serial rapid input/output (SRIO) endpoint
#17 | 2009-04-02Non-Random Access Rapid I/O Endpoint In A Multi-Processor System
#18 | 2009-04-02Multi-function queue to support data offload, protocol translation and pass-through FIFO
#19 | 2008-08-28Rapid input/output doorbell coalescing to minimize CPU utilization and reduce system interrupt latency
#20 | 2008-08-28Hardware-based concurrent direct memory access (DMA) engines on serial rapid input/output SRIO interface
#21 | 2008-08-28Multi-bus structure for optimizing system performance of a serial buffer
#22 | 2008-08-28Method and structure to support system resource access of a serial device implementating a lite-weight protocol
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