Inventor profile of:

Patrick James Meaney

City:

Poughkeepsie, New York

Country:

United States

Published Applications:

15

Last publication date:

2026-03-26

Top Assignees for applications by Patrick James Meaney

The entities that hold a legal rights for patent applications filed by inventor Meaney Patrick James:

Recent patent applications by Meaney Patrick James

Patrick James Meaney from Poughkeepsie, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-03-26
US20260088995A1
Electricity

DYNAMIC KEY REASSIGNMENT FOR MEMORY ENCRYPTION KEYS

#2 | 2026-03-12
US20260072594A1
Physics

CANCELLING UNUSED READ COMMANDS FOR ACCESSING DATA IN MEMORY

#3 | 2025-12-11
US20250377958A1
Physics

COMPONENT ROTATION

#4 | 2024-12-05
US20240402246A1
Physics

Error protection analysis of an integrated circuit

#5 | 2024-09-19
US20240311260A1
Physics

DYNAMIC MULTI-LANE DEGRADE CAPABILITY TO FACILITATE UNINTERRUPTED SERVICE

#6 | 2024-03-28
US20240103967A1
Physics

Memory Decoder Providing Optimized Error Detection and Correction for Data Distributed Across Memory Channels

#7 | 2023-12-07
US20230393999A1
Physics

Cable pair concurrent servicing

#8 | 2023-04-13
US20230115533A1
Physics

Low-latency deserializer having fine granularity and defective-lane compensation

#9 | 2023-03-30
US20230098514A1
Electricity

Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes

#10 | 2021-12-30
US20210406126A1
Physics

Low latency availability in degraded redundant array of independent memory

#11 | 2021-07-15
US20210216401A1
Physics

Refresh-hiding memory system staggered refresh

#12 | 2021-07-15
US20210216400A1
Physics

Low latency availability in degraded redundant array of independent memory

#13 | 2009-08-27
US20090217115A1
Physics

Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy

#14 | 2009-08-20
US20090210843A1
Physics

Method of automating creation of a clock control distribution network in an integrated circuit floorplan

#15 | 2009-04-23
US20090106607A1
Physics

Method and apparatus for SRAM macro sparing in computer chips

InventorID:

3931616 ⎘