Steven M. Thurber

Configurable I/O address translation data structure

Configurable I/O address translation data structure

Memory mapped input/output bus address range translation

Dynamic allocation of a direct memory address window

Implementing PCI-express memory domains for single root virtualized devices

Moving ownership of a device between compute elements

Memory mapped input/output bus address range translation for virtual bridges

Memory mapped input/output bus address range translation

Hierarchical to physical memory mapped input/output translation

Translating a requester identifier to a chip identifier

Hierarchical to physical bus translation

Physical to hierarchical bus translation

Differentiating blade destination and traffic types in a multi-root PCIe environment

Use of peripheral component interconnect input/output virtualization devices to create redundant configurations

Differentiating traffic types in a multi-root PCI express environment

Use of peripheral component interconnect input/output virtualization devices to create high-speed, low-latency interconnect

PCI function south-side data management

Multi-root I/O virtualization using separate management facilities of multiple logical partitions

Retaining an association between a virtual address based buffer and a user space application that owns the buffer

Native and non-native I/O virtualization in a single adapter

Mapping a virtual address to PCI bus address

Distribution of resources for I/O virtualized (IOV) adapters and management of the adapters through an IOV management partition via user selection of compatible virtual functions

PCI express address translation services invalidation synchronization with TCE invalidation

Management of an IOV adapter through a virtual intermediary in a hypervisor with functional management in an IOV management partition

Management of an IOV adapter through a virtual intermediary in an IOV management partition

Broadcast of shared I/O fabric error messages in a multi-host environment to all affected root nodes

Method, apparatus, and computer usable program code for migrating virtual adapters from source physical adapters to destination physical adapters

Routing Mechanism in PCI Multi-Host Topologies Using Destination ID Field

Method of routing I/O adapter error messages in a multi-host environment

Method, apparatus, and computer program product for routing packets utilizing a unique identifier, included within a standard address, that identifies the destination host computer system

Method using a master node to control I/O fabric configuration in a multi-host environment

Creation and management of routing table for PCI bus address based routing with integrated DID

Method for communicating with a network adapter using a queue data structure and cached address translations

Isolation of input/output adapter error domains

Migration of single root stateless virtual functions

Communication between host systems using a queuing system and shared memories

Communicating with an I/O device using a queue data structure and pre-translated addresses

Initializing shared memories for sharing endpoints across a plurality of root complexes

Migration of a virtual endpoint from one virtual plane to another

Communication between host systems using a transaction protocol and shared memories

Hot-plug/remove of a new component in a running PCIe fabric

Communication between host systems using a socket connection and shared memories

System and method for configuring an endpoint based on specified valid combinations of functions

Migrating stateless virtual functions from one virtual plane to another

Creation and management of destination ID routing structures in multi-host PCI topologies

Bus/device/function translation within and routing of communications packets in a PCI switched-fabric in a multi-host environment utilizing multiple root switches

BUS/DEVICE/FUNCTION TRANSLATION WITHIN AND ROUTING OF COMMUNICATIONS PACKETS IN A PCI SWITCHED-FABRIC IN A MULTI-HOST ENVIRONMENT ENVIRONMENT UTILIZING A ROOT SWITCH

METHOD, SYSTEM, AND APPARATUS FOR ENHANCED MANAGEMENT OF MESSAGE SIGNALED INTERRUPTS

Splitting endpoint address translation cache management responsibilities between a device driver and device driver services

Communicating with a memory registration enabled adapter using cached address translations

Method for communicating with an I/O adapter using cached address translations

Method, apparatus, and computer usable program code for migrating virtual adapters from source physical adapters to destination physical adapters

Method, apparatus, and computer program product for routing packets utilizing a unique identifier, included within a standard address, that identifies the destination host computer system

Routing of shared I/O fabric error messages in a multi-host environment to a master control root node

Creation and management of routing table for PCI bus address based routing with integrated DID

Creation and management of ATPT in switches of multi-host PCI topologies

Method for confirming identity of a master node selected to control I/O fabric configuration in a multi-host environment

Routing mechanism in PCI multi-host topologies using destination ID field

Method using a master node to control I/O fabric configuration in a multi-host environment

Creation and management of destination ID routing structures in multi-host PCI topologies

Method of routing I/O adapter error messages in a multi-host environment

Broadcast of shared I/O fabric error messages in a multi-host environment to all affected root nodes

Mechanism to virtualize all address spaces in shared I/O fabrics