Inventor profile of:

Pranay Koka

City:

Austin, Texas

Country:

United States

Published Applications:

33

Last publication date:

2016-05-05

Top Assignees for applications by Pranay Koka

The entities that hold a legal rights for patent applications filed by inventor Koka Pranay:

Recent patent applications by Koka Pranay

Pranay Koka from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2016-05-05
US20160124858A1
Physics

Method and system for dynamic cache partitioning using address remapping

#2 | 2016-03-03
US20160062894A1
Physics

System and method for performing message driven prefetching at the network interface

#3 | 2016-02-11
US20160043977A1
Electricity

Data deduplication at the network interfaces

#4 | 2015-10-22
US20150301949A1
Physics

Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with optical interconnect

#5 | 2015-03-12
US20150071632A1
Electricity

Reconfigurable optical interconnect network

#6 | 2014-09-18
US20140269751A1
Electricity

Prediction-based switch allocator

#7 | 2014-05-15
US20140133861A1
Electricity

Opportunistic bandwidth stealing in optical networks

#8 | 2014-05-01
US20140122802A1
Physics

Accessing an off-chip cache via silicon photonic waveguides

#9 | 2014-05-01
US20140119738A1
Electricity

SINGLE-LAYER OPTICAL POINT-TO-POINT NETWORK

#10 | 2014-03-27
US20140089572A1
Physics

Distributed page-table lookups in a shared-memory system

#11 | 2014-02-20
US20140052917A1
Physics

Using a shared last-level TLB to reduce address-translation latency

#12 | 2014-02-06
US20140040562A1
Physics

Using broadcast-based TLB sharing to reduce address-translation latency in a shared-memory system with electrical interconnect

#13 | 2014-01-09
US20140013074A1
Physics

Combining a remote TLB lookup and a subsequent cache miss into a single coherence operation

#14 | 2013-11-21
US20130308944A1
Physics

Butterfly optical network with crossing-free switches

#15 | 2013-06-06
US20130145086A1
Physics

Processor-bus-connected flash storage paging device using a virtual memory mapping table and page faults

#16 | 2013-01-17
US20130016980A1
Electricity

Optical network with tunable optical light sources

#17 | 2013-01-17
US20130016970A1
Physics

Optical network with switchable drop filters

#18 | 2013-01-17
US20130016941A1
Physics

Arbitrated optical network using tunable drop filters

#19 | 2012-05-03
US20120110251A1
Physics

Executing flash storage access requests

#20 | 2011-08-18
US20110200335A1
Electricity

Data channel organization for a switched arbitrated on-chip optical network

#21 | 2011-08-18
US20110200332A1
Electricity

Shared-source-row optical data channel organization for a switched arbitrated on-chip optical network

#22 | 2011-07-21
US20110179208A1
Electricity

Time division multiplexing based arbitration for shared optical links

#23 | 2011-05-05
US20110103397A1
Electricity

Two-phase arbitration mechanism for shared optical links

#24 | 2011-04-21
US20110093646A1
Physics

Processor-bus attached flash main-memory module

#25 | 2011-04-07
US20110082965A1
Physics

Processor-bus-connected flash storage nodes with caching to support concurrent DMA accesses from multiple processors

#26 | 2010-10-26
US11685555
-

Hardware data race detection in HPCS codes

#27 | 2010-10-21
US20100266277A1
Electricity

Data transmission using direct and indirect optical paths

#28 | 2010-01-21
US20100017572A1
Physics

Transactional memory support for non-coherent shared memory systems using selective write through caches

#29 | 2010-01-21
US20100014852A1
Electricity

Collision detection scheme for optical interconnects

#30 | 2010-01-21
US20100014427A1
Electricity

Arbitration scheme for an optical bus

#31 | 2009-04-02
US20090089511A1
Physics

Hybrid cache coherence using fine-grained hardware message passing

#32 | 2009-04-02
US20090086746A1
Physics

Direct messaging in distributed memory systems

#33 | 2008-10-02
US20080244185A1
Physics

Reduction of cache flush time using a dirty line limiter

InventorID:

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