Cupertino, California
United States
47
2015-06-09
The entities that hold a legal rights for patent applications filed by inventor Joshi Rajeev:
Rajeev Joshi from Cupertino, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Method of forming a magnetics package
#2 | 2014-06-19Semiconductor die package and method for making the same
#3 | 2013-08-29Integrated circuit package including an embedded power stage wherein a first field effect transistor (FET) and a second FET are electrically coupled therein
#4 | 2013-08-22DC/DC converter power module package incorporating a stacked controller and construction methodology
#5 | 2012-12-27DC/DC CONVERTOR POWER MODULE PACKAGE INCORPORATING A STACKED CONTROLLER AND CONSTRUCTION METHODOLOGY
#6 | 2012-12-25Leadframe based magnetics package
#7 | 2012-07-19Semiconductor die package and method for making the same
#8 | 2012-03-15SEMICONDUCTOR DIE PACKAGE INCLUDING MULTIPLE DIES AND A COMMON NODE STRUCTURE
#9 | 2010-10-14Semiconductor die package and method for making the same
#10 | 2010-04-15Semiconductor die package including multiple dies and a common node structure
#11 | 2009-09-17High performance multi-chip flip chip package
#12 | 2009-07-23Dual metal stud bumping for flip chip applications
#13 | 2009-05-26High performance multi-chip flip chip package
#14 | 2009-05-21Substrate based unmolded package
#15 | 2009-02-05Method of providing a RF shield of an electronic device
#16 | 2008-10-21Substrate based unmolded package
#17 | 2008-09-04Substrate based unmolded package
#18 | 2008-08-14Leadframe based photo voltaic electronic assembly
#19 | 2008-05-08Thin, thermally enhanced flip chip in a leaded molded package
#20 | 2008-02-14Flip chip in leaded molded package and method of manufacture thereof
#21 | 2007-10-25Semiconductor die package including multiple dies and a common node structure
#22 | 2007-09-18Dual metal stud bumping for flip chip applications
#23 | 2007-03-29Method of assembly for multi-flip chip on lead frame on overmolded IC package
#24 | 2007-01-04Semiconductor die package and method for making the same
#25 | 2006-12-21Lead frame structure with aperture or groove for flip chip in a leaded molded package
#26 | 2006-08-24Dual metal stud bumping for flip chip applications
#27 | 2006-07-13Method to manufacture a universal footprint for a package with exposed chip
#28 | 2006-06-13Substrate based unmolded package including lead frame structure and semiconductor die
#29 | 2006-04-18Flip chip in leaded molded package with two dies
#30 | 2006-04-04Method for making a semiconductor die package
#31 | 2006-03-07Passivation scheme for bumped wafers
#32 | 2006-01-31High performance multi-chip flip chip package
#33 | 2006-01-12Substrate based unmolded package
#34 | 2006-01-05Substrate based unmolded package
#35 | 2005-12-22Unmolded package for a semiconductor device
#36 | 2005-12-22Flip chip in leaded molded package and method of manufacture thereof
#37 | 2005-10-11Unmolded package for a semiconductor device
#38 | 2005-10-06Surface mount multi-channel optocoupler
#39 | 2005-09-27Flip chip in leaded molded package and method of manufacture thereof
#40 | 2005-09-22Multi-flip chip on lead frame on over molded IC package and method of assembly
#41 | 2005-08-11Wafer-level chip scale package and method for fabricating and using the same
#42 | 2005-08-04Flip chip in leaded molded package and method of manufacture thereof
#43 | 2005-06-23Lead frame structure with aperture or groove for flip chip in a leaded molded package
#44 | 2005-06-16Thin, thermally enhanced molded package with leadframe having protruding region
#45 | 2005-05-10Thin, thermally enhanced flip chip in a leaded molded package
#46 | 2005-03-15Lead frame structure with aperture or groove for flip chip in a leaded molded package
#47 | 2005-03-10Flip chip substrate design
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