Eagle, Idaho
United States
149
2026-03-19
The entities that hold a legal rights for patent applications filed by inventor Kirby Kyle K.:
Kyle K. Kirby from Eagle, US has applied for patents for these inventions. The list has both pending applications and granted patents:
MONOLITHIC CONDUCTIVE CYLINDER IN A SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS
#2 | 2026-03-19SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT
#3 | 2026-03-05GRINDABLE HEAT SINK FOR MULTIPLE DIE PACKAGING
#4 | 2026-02-05SYSTEMS AND METHODS FOR DIRECT BONDING IN SEMICONDUCTOR DIE MANUFACTURING
#5 | 2026-01-08HYBRID BONDING OF SEMICONDUCTOR CMOS WAFER AND SEMICONDUCTOR MEMORY ARRAY WAFER USING DEBONDABLE CARRIERS
#6 | 2026-01-08THREE-DIMENSIONAL CLEAVAGE TECHNIQUES USING STEALTH DICING, AND ASSOCIATED SYSTEMS AND METHODS
#7 | 2025-12-25HETEROGENOUS INTEGRATION OF SEMICONDUCTOR STRUCTURES
#8 | 2025-11-27FRONT END OF LINE INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS
#9 | 2025-11-13FACILITATING WAFER DEBONDING BY INTRODUCING MOISTURE TO BONDING INTERFACE
#10 | 2025-11-13CORROSION-SUSCEPTIBLE BONDING LAYER IN ASSISTING SEMICONDUCTOR WAFER DEBONDING
#11 | 2025-10-30MONOLITHIC CONDUCTIVE COLUMN IN A SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS
#12 | 2025-10-23MICROELECTRONIC DEVICES, AND RELATED METHODS AND MEMORY DEVICES
#13 | 2025-09-18FRONT END OF LINE INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS
#14 | 2025-09-11PIEZOELECTRIC MATERIALS FOR ON-DIE THERMAL ENHANCEMENT OF HYBRID BONDING AND ASSOCIATED SYSTEMS AND METHODS
#15 | 2025-06-12SEMICONDUCTOR WAFER WITH RECESSED PORTIONS AT A SCRIBE AREA
#16 | 2025-05-01MONOLITHIC CONDUCTIVE COLUMNS IN A SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS
#17 | 2025-04-24ALIGNMENT MARKERS FOR WAFER BONDING AND ASSOCIATED SYSTEMS AND METHODS
#18 | 2025-01-16FRONT END OF LINE INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS
#19 | 2024-12-05MICROELECTRONIC DEVICES WITH THROUGH-SUBSTRATE INTERCONNECTS AND ASSOCIATED METHODS OF MANUFACTURING
#20 | 2024-11-14SEMICONDUCTOR MEMORY STACKS CONNECTED TO PROCESSING UNITS AND ASSOCIATED SYSTEMS AND METHODS
#21 | 2024-11-14MONOLITHIC CONDUCTIVE COLUMN IN A SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS
#22 | 2024-10-03SEMICONDUCTOR DEVICE WITH DUAL DAMASCENE AND DUMMY PADS
#23 | 2024-08-22HIGH DENSITY PILLAR INTERCONNECT CONVERSION WITH STACK TO SUBSTRATE CONNECTION
#24 | 2024-08-22HYBRID BONDING FOR SEMICONDUCTOR DEVICE ASSEMBLIES
#25 | 2024-08-22SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT
#26 | 2024-07-11INDUCTORS WITH THROUGH-SUBSTRATE VIA CORES
#27 | 2024-07-04SEMICONDUCTOR INTERCONNECT STRUCTURES WITH VERTICALLY OFFSET BONDING SURFACES, AND ASSOCIATED SYSTEMS AND METHODS
#28 | 2024-04-25FRONT END OF LINE INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS
#29 | 2024-03-14FRONT END OF LINE INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS
#30 | 2024-03-07CONNECTING SEMICONDUCTOR DIES THROUGH TRACES
#31 | 2024-02-29SEMICONDUCTOR DEVICE WITH CIRCUIT COMPONENTS FORMED THROUGH INTER-DIE CONNECTIONS
#32 | 2024-02-29SEMICONDUCTOR DEVICE CIRCUITRY FORMED FROM REMOTE RESERVOIRS
#33 | 2024-02-29EMBEDDED NANOPARTICLES FOR ON-DIE THERMAL ENHANCEMENT OF HYBRID BONDING AND ASSOCIATED SYSTEMS AND METHODS
#34 | 2024-02-29PIEZOELECTRIC MATERIALS FOR ON-DIE THERMAL ENHANCEMENT OF HYBRID BONDING AND ASSOCIATED SYSTEMS AND METHODS
#35 | 2024-02-29SEMICONDUCTOR DEVICE WITH VOLUMETRICALLY-EXPANDED SIDE-CONNECTED INTERCONNECTS
#36 | 2024-02-29SEMICONDUCTOR DIE STACKS AND ASSOCIATED SYSTEMS AND METHODS
#37 | 2024-02-29SEMICONDUCTOR DEVICE INTERCONNECTS FORMED THROUGH VOLUMETRIC EXPANSION
#38 | 2024-02-29SEMICONDUCTOR DEVICE CIRCUITRY FORMED THROUGH VOLUMETRIC EXPANSION
#39 | 2024-02-22METHODS FOR FUSION BONDING SEMICONDUCTOR DEVICES TO TEMPORARY CARRIER WAFERS WITH CAVITY REGIONS FOR REDUCED BOND STRENGTH, AND SEMICONDUCTOR DEVICE ASSEMBLIES FORMED BY THE SAME
#40 | 2024-02-15SUBSTRATE FOR VERTICALLY ASSEMBLED SEMICONDUCTOR DIES
#41 | 2023-12-07Semiconductor memory stacks connected to processing units and associated systems and methods
#42 | 2023-08-17Monolithic conductive columns in a semiconductor device and associated methods
#43 | 2023-08-17MONOLITHIC CONDUCTIVE CYLINDER IN A SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS
#44 | 2023-08-17MONOLITHIC CONDUCTIVE COLUMN IN A SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS
#45 | 2023-08-17Monolithic conductive column in a semiconductor device and associated methods
#46 | 2023-07-27Grindable heat sink for multiple die packaging
#47 | 2023-06-22High density pillar interconnect conversion with stack to substrate connection
#48 | 2023-06-22Semiconductor interconnect structures with vertically offset bonding surfaces, and associated systems and methods
#49 | 2023-06-01Multi-height interconnect structures and associated systems and methods
#50 | 2023-03-02SYSTEMS AND METHODS FOR DIRECT BONDING IN SEMICONDUCTOR DIE MANUFACTURING
#51 | 2023-03-02EXOTHERMIC REACTIVE BONDING FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED SYSTEMS AND METHODS
#52 | 2023-03-02CASTELLATION, HATCHING, AND OTHER SURFACE PATTERNS IN DIELECTRIC SURFACES FOR HYBRID BONDING WITH INCREASED SURFACE AREA, BOND STRENGTH, AND ALIGNMENT
#53 | 2023-02-16ELASTIC BONDING LAYERS FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED SYSTEMS AND METHODS
#54 | 2022-10-27Semiconductor interconnect structures with vertically offset bonding surfaces, and associated systems and methods
#55 | 2022-10-20MICROELECTRONIC DEVICES WITH THROUGH-SUBSTRATE INTERCONNECTS AND ASSOCIATED METHODS OF MANUFACTURING
#56 | 2022-08-04Combination-bonded die pair packaging and associated systems and methods
#57 | 2022-05-19Semiconductor die stacks and associated systems and methods
#58 | 2022-05-19Semiconductor memory stacks connected to processing units and associated systems and methods
#59 | 2022-03-31Combination-bonded die pair packaging and associated systems and methods
#60 | 2022-03-03Front end of line interconnect structures and associated systems and methods
#61 | 2022-03-03Front end of line interconnect structures and associated systems and methods
#62 | 2022-03-03Front end of line interconnect structures and associated systems and methods
#63 | 2022-01-27Semiconductor die stacks and associated systems and methods
#64 | 2022-01-27Semiconductor memory stacks connected to processing units and associated systems and methods
#65 | 2021-11-11High density pillar interconnect conversion with stack to substrate connection
#66 | 2021-08-05Multi-height interconnect structures and associated systems and methods
#67 | 2021-08-05INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS
#68 | 2021-07-22High density pillar interconnect conversion with stack to substrate connection
#69 | 2021-07-013DI solder cup
#70 | 2021-06-17Semiconductor device assembly with pillar array
#71 | 2021-05-06High density pillar interconnect conversion with stack to substrate connection
#72 | 2021-05-06High density pillar interconnect conversion with stack to substrate connection
#73 | 2021-05-06Encapsulated solder TSV insertion interconnect
#74 | 2021-04-08Semiconductor devices with back-side coils for wireless signal and power coupling
#75 | 2021-03-18Inductors with through-substrate via cores
#76 | 2021-02-25Semiconductor with through-substrate interconnect
#77 | 2020-10-01Microelectronic devices with through-substrate interconnects and associated methods of manufacturing
#78 | 2020-09-17VIAS AND CONDUCTIVE ROUTING LAYERS IN SEMICONDUCTOR SUBSTRATES
#79 | 2020-02-273DI solder cup
#80 | 2019-12-05Semiconductor devices with underfill control features, and associated systems and methods
#81 | 2019-11-07Semiconductor device assembly with pillar array and test ability
#82 | 2019-06-06Semiconductor device assembly with pillar array
#83 | 2019-05-023DI solder cup
#84 | 2019-02-14Methods for forming interconnect assemblies with probed bond pads
#85 | 2019-01-243D interconnect multi-die inductors with through-substrate via cores
#86 | 2018-11-29Microelectronic devices and methods for filling vias in microelectronic devices
#87 | 2018-11-08INDUCTORS WITH THROUGH-SUBSTRATE VIA CORES
#88 | 2018-11-08SEMICONDUCTOR DEVICES WITH THROUGH-SUBSTRATE COILS FOR WIRELESS SIGNAL AND POWER COUPLING
#89 | 2018-11-083D interconnect multi-die inductors with through-substrate via cores
#90 | 2018-11-08Multi-die inductors with coupled through-substrate via cores
#91 | 2018-11-083D interconnect multi-die inductors with through-substrate via cores
#92 | 2018-11-08Multi-die inductors with coupled through-substrate via cores
#93 | 2018-11-08Semiconductor devices with back-side coils for wireless signal and power coupling
#94 | 2018-06-14Semiconductor with through-substrate interconnect
#95 | 2018-05-03Semiconductor devices with underfill control features, and associated systems and methods
#96 | 2017-12-28Vias and conductive routing layers in semiconductor substrates
#97 | 2017-10-19MICROELECTRONIC DEVICES AND METHODS FOR FILLING VIAS IN MICROELECTRONIC DEVICES
#98 | 2017-07-27Semiconductor with through-substrate interconnect
#99 | 2017-07-20Methods for forming interconnect assemblies with probed bond pads
#100 | 2017-03-16Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
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