Inventor profile of:

Ming Hung Wang

City:

Hsinchu

Country:

Taiwan

Published Applications:

19

Last publication date:

2025-07-10

Top Assignees for applications by Ming Hung Wang

The entities that hold a legal rights for patent applications filed by inventor Wang Ming Hung:

Recent patent applications by Wang Ming Hung

Ming Hung Wang from Hsinchu, TW has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-07-10
US20250226052A1
Physics

METHOD AND CIRCUITRY FOR HANDLING DEFECTIVE MEMORY CELLS AND WORDLINES IN MEMORY MODULE

#2 | 2022-04-28
US20220130450A1
Physics

DRAM with inter-section, page-data-copy scheme for low power and wide data access

#3 | 2022-03-31
US20220100816A1
Physics

Apparatus for data processing in conjunction with memory array access

#4 | 2022-02-15
US17037755
Physics

DRAM with inter-section, page-data-copy scheme for low power and wide data access

#5 | 2021-05-27
US20210158856A1
Physics

Apparatus for enhancing prefetch access in memory module

#6 | 2021-05-27
US20210158853A1
Physics

Method and apparatus for accumulating and storing respective access counts of word lines in memory module

#7 | 2018-03-08
US20180068700A1
Physics

Memory architecture with multi-bank memory cell array accessed by local drive circuit within memory bank

#8 | 2017-05-16
US15047605
Physics

Multi-bank memory device and system

#9 | 2012-09-13
US20120229146A1
Physics

High speed test circuit and method

#10 | 2009-07-09
US20090175101A1
Physics

Self-feedback control pipeline architecture for memory read path applications

#11 | 2008-12-11
US20080304332A1
Physics

Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application

#12 | 2008-12-11
US20080304331A1
Physics

Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application

#13 | 2008-11-20
US20080285363A1
Physics

Self-feedback control pipeline architecture for memory read path applications

#14 | 2008-07-31
US20080180181A1
Electricity

Ring oscillator with a two-stage phase blender for generating multi-phase clock signals

#15 | 2008-06-19
US20080142924A1
Electricity

Decoupling capacitor circuit

#16 | 2008-02-07
US20080031064A1
Physics

Self-feedback control pipeline architecture for memory read path applications

#17 | 2007-10-18
US20070241794A1
Electricity

Comparator circuit with Schmitt trigger hysteresis character

#18 | 2006-07-06
US20060146636A1
Physics

Internal power management scheme for a memory chip in deep power down mode

#19 | 2005-12-08
US20050270880A1
Physics

Internal power management scheme for a memory chip in deep power down mode

InventorID:

3983813 ⎘