Toronto
Canada
40
2024-01-04
The entities that hold a legal rights for patent applications filed by inventor Leventis Paul:
Paul Leventis from Toronto, CA has applied for patents for these inventions. The list has both pending applications and granted patents:
MEMORY MANAGEMENT IN GAMING RENDERING
#2 | 2023-10-19METHODS AND SYSTEMS FOR RENDERING AND ENCODING CONTENT FOR ONLINE INTERACTIVE GAMING SESSIONS
#3 | 2022-02-24Methods and systems for rendering and encoding content for online interactive gaming sessions
#4 | 2021-11-25Shadow tracking of real-time interactive simulations for complex system analysis
#5 | 2021-07-15Memory management in gaming rendering
#6 | 2020-07-30Methods and systems for rendering and encoding content for online interactive gaming sessions
#7 | 2020-07-23Distributed sample-based game profiling with game metadata and metrics and gaming API platform supporting third-party content
#8 | 2019-10-24Resolution-based scaling of real-time interactive graphics
#9 | 2019-10-10Memory management in gaming rendering
#10 | 2014-07-31PLD architecture for flexible placement of IP function blocks
#11 | 2013-08-22PLD architecture for flexible placement of IP function blocks
#12 | 2013-05-14Pessimism removal in the modeling of simultaneous switching noise
#13 | 2012-08-30PLD architecture for flexible placement of IP function blocks
#14 | 2012-05-29Redundancy structures and methods in a programmable logic device
#15 | 2012-04-12Apparatus and Methods for Optimizing the Performance of Programmable Logic Devices
#16 | 2012-01-17Power-driven timing analysis and placement for programmable logic
#17 | 2011-07-19Simultaneous switching noise analysis using superposition techniques
#18 | 2010-12-28Power-driven timing analysis and placement for programmable logic
#19 | 2010-03-02Versatile logic element and logic array block
#20 | 2009-09-10PLD architecture for flexible placement of IP function blocks
#21 | 2008-10-23Apparatus and methods for optimizing the performance of programmable logic devices using multiple supply voltage
#22 | 2008-09-25Distributed memory in field-programmable gate array integrated circuit devices
#23 | 2007-12-04Distributed random access memory in a programmable logic device
#24 | 2007-11-01Versatile logic element and logic array block
#25 | 2007-08-07Multiplexing device including a hardwired multiplexer in a programmable logic device
#26 | 2007-06-28Distributed memory in field-programmable gate array integrated circuit devices
#27 | 2007-06-26Data compression and decompression techniques for programmable circuits
#28 | 2007-02-27Method and apparatus for enhancing signal routability
#29 | 2007-02-22Apparatus and methods for optimizing the performance of programmable logic devices
#30 | 2006-08-29Flexible routing resources in a programmable logic device
#31 | 2006-08-01Distributed random access memory in a programmable logic device
#32 | 2006-06-06Methods for designing PLD architectures for flexible placement of IP function blocks
#33 | 2006-02-16PLD architecture for flexible placement of IP function blocks
#34 | 2005-12-01Redundancy structures and methods in a programmable logic device
#35 | 2005-11-29Routing architecture for a programmable logic device
#36 | 2005-10-20Routing architecture with high speed I/O bypass path
#37 | 2005-08-30Versatile logic element and logic array block
#38 | 2005-06-16Versatile logic element and logic array block
#39 | 2005-05-17System and method for optimizing routing lines in a programmable logic device
#40 | 2005-02-22Use of dangling partial lines for interfacing in a PLD
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