Boise, Idaho
United States
33
2026-02-05
The entities that hold a legal rights for patent applications filed by inventor Guha Jaydip:
Jaydip Guha from Boise, US has applied for patents for these inventions. The list has both pending applications and granted patents:
MEMORY DEVICES WITH BURIED DIGIT LINES
#2 | 2025-08-28Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors
#3 | 2025-04-17MEMORY DEVICE INCLUDING CALIBRATION OPERATION AND TRANSISTOR HAVING ADJUSTABLE THRESHOLD VOLTAGE
#4 | 2024-02-29MEMORY ARRAY - PERIPHERY INTEGRATION WITH SPLIT BARRIER METAL STACK
#5 | 2024-02-29CONDUCTIVE STRUCTURES
#6 | 2023-12-07MEMORY DEVICE HAVING CONTROL GATE DIELECTRIC STRUCTURE WITH DIFFERENT DIELECTRIC MATERIALS
#7 | 2023-03-02Recessed access devices and methods of forming a recessed access devices
#8 | 2023-03-02Recessed Access Devices And Methods Of Forming A Recessed Access Devices
#9 | 2023-01-19Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors
#10 | 2022-09-29Memory device including calibration operation and transistor having adjustable threshold voltage
#11 | 2022-03-03Integrated assemblies and methods of forming integrated assemblies
#12 | 2022-03-03Integrated assemblies and methods of forming integrated assemblies
#13 | 2022-01-27Array of vertical transistors and method used in forming an array of vertical transistors
#14 | 2020-12-31Apparatus with doped surfaces, and related methods with in situ doping
#15 | 2018-06-21Conductive structures, wordlines and transistors
#16 | 2018-05-17Conductive structures, wordlines and transistors
#17 | 2015-09-03Memory Cells and Methods Of Forming Memory Cells
#18 | 2015-07-23Methods of forming memory arrays and semiconductor constructions
#19 | 2015-01-15Memory arrays, semiconductor constructions, and methods of forming semiconductor constructions
#20 | 2015-01-01Gate Constructions Of Recessed Access Devices And Methods Of Forming Gate Constructions Of Recessed Access Devices
#21 | 2014-12-23Method of manufacturing sidewall spacers on a memory device
#22 | 2014-10-23Methods of forming a vertical transistor
#23 | 2014-03-13Methods of forming a vertical transistor, methods of forming memory cells, and methods of forming arrays of memory cells
#24 | 2014-02-27Methods of forming memory arrays and semiconductor constructions
#25 | 2014-01-16Methods of forming semiconductor constructions
#26 | 2013-09-12Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith
#27 | 2013-06-27Method of manufacturing sidewall spacers on a memory device
#28 | 2013-04-11Memory cells having capacitor dielectric directly against a transistor source/drain region
#29 | 2013-01-03Memory cells, arrays of memory cells, and methods of forming memory cells
#30 | 2012-11-29Integrated circuit arrays and semiconductor constructions
#31 | 2012-08-23Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith
#32 | 2012-05-03Memory cells, arrays of memory cells, and methods of forming memory cells
#33 | 2012-01-12Gate constructions of recessed access devices and methods of forming gate constructions of recessed access devices
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