Grenoble
France
8
2026-04-30
The entities that hold a legal rights for patent applications filed by inventor Brunet Laurent:
Laurent Brunet from Grenoble, FR has applied for patents for these inventions. The list has both pending applications and granted patents:
METHOD FOR MANUFACTURING COMBINED FD-SOI PFET AND NFET TRANSISTORS
#2 | 2019-06-27Assembly for 3D circuit with superposed transistor levels
#3 | 2018-03-29Integrated circuit having a plurality of active layers and method of fabricating the same
#4 | 2017-12-28Process for fabricating a transistor structure including a plugging step
#5 | 2017-08-03Method of manufacturing a dopant transistor located vertically on the gate
#6 | 2017-06-22Fabrication method of a stack of electronic devices
#7 | 2013-08-22Method and device for measuring changes over time of the electrical performance of an FDSOI transistor
#8 | 2011-03-03Method and device for evaluating electric performances of an FDSOI transistor
404853 ⎘