PHILIP R. GERMANN

Residual material detection in backdrilled stubs

Residual material detection in backdrilled stubs

Residual material detection in backdrilled stubs

Intelligent chip placement within a three-dimensional chip stack

Intelligent chip placement within a three-dimensional chip stack

Donor cores to improve integrated circuit yield

Interconnect solder bumps for die testing

Implementing semiconductor signal-capable capacitors with deep trench and TSV technologies

Implementing memory interface with configurable bandwidth

Implementing selective rework for chip stacks and silicon carrier assemblies

IMPLEMENTING INTERLEAVED-DIELECTRIC JOINING OF MULTI-LAYER LAMINATES

Through silicon via direct FET signal gating

Field-effect transistor and method of creating same

Power domain controller with gated through silicon via having FET with horizontal channel

Implementing interleaved-dielectric joining of multi-layer laminates

Sorting movable memory hierarchies in a computer system

Continuity check monitoring for microchip exploitation detection

Signal quality monitoring to defeat microchip exploitation

Capacitance-based microchip exploitation detection

Interdependent Microchip Functionality for Defeating Exploitation Attempts

False connection for defeating microchip exploitation

Resistance sensing for defeating microchip exploitation

Capacitance structures for defeating microchip tampering

SHIELDED WIREBOND

Doped implant monitoring for microchip tamper detection

System and Method for Thermal Optimized Chip Stacking

Techniques for providing switchable decoupling capacitors for an integrated circuit

Method and structure for dispensing chip underfill through an opening in the chip

METHOD AND APPARATUS TO TEST ELECTRICAL CONTINUITY AND REDUCE LOADING PARASITICS ON HIGH-SPEED SIGNALS

BIMETALLIC HEAT SINK AIR DEFLECTORS FOR DIRECTED AIRFLOW FOR IMPROVED THERMAL TRANSFER AND DISSIPATION

System and method for implementing optimized creation of openings for de-gassing in an electronic package

Spider web interconnect topology utilizing multiple port connection

METHOD AND COMPUTER PROGRAM FOR AUTOMATED ASSIGNMENT AND INTERCONNECTION OF DIFFERENTIAL PAIRS WITHIN AN ELECTRONIC PACKAGE

Structure for multi-level memory architecture with data prioritization

Using common mode differential data signals of DDR2 SDRAM for control signal transmission

Dynamic latency map for memory optimization

Multi-level memory architecture with data prioritization

Using common mode differential data signals of DDR2 SDRAM for control signal transmission