JOHN E. SHEETS, II

PROCESSOR CHIP TIMING ADJUSTMENT ENHANCEMENT

Negative operand compatible charge-scaling subtractor circuit

Charge-scaling multiplier circuit with digital-to-analog converter

Charge-scaling multiplier circuit with dual scaled capacitor sets

Charge-scaling multiplier circuit

Low resistance contact for transistors

Charge-scaling subtractor circuit

Charge-scaling adder circuit

Semiconductor device and method of forming the semiconductor device

Managed integrated circuit power supply distribution

Low resistance contact for transistors

Charge-scaling subtractor circuit

Charge-scaling adder circuit

Managed integrated circuit power supply distribution

Metalization repair in semiconductor wafers

Through-substrate via power gating and delivery bipolar transistor

Through-substrate via power gating and delivery bipolar transistor

Optimizing data approximation analysis using low power circuitry

Optimizing data approximation analysis using low bower circuitry

Real time cognitive reasoning using a circuit with varying confidence level alerts

Real time cognitive reasoning using a circuit with varying confidence level alerts

Real time cognitive monitoring of correlations between variables

Cognitive analysis using applied analog circuits

Real time cognitive monitoring of correlations between variables

Cognitive analysis using applied analog circuits

Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells

Optimizing data approximation analysis using low power circuitry

Optimizing data approximation analysis using low power circuitry

Method for low power operation and test using DRAM device

Optimizing data approximation analysis using low power circuitry

Method of optimizing wire RC for device performance and reliability

Generating a unique die identifier for an electronic chip

Integrated shielding and decoupling capacitor structure

Semiconductor device and method of forming the semiconductor device

Metalization repair in semiconductor wafers

Semiconductor device and method of forming the semiconductor device

METALIZATION REPAIR IN SEMICONDUCTOR WAFERS

Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells

Generating a unique die identifier for an electronic chip

Enhancing performance of one or more slower partitions of an integrated circuit to improve performance of the integrated circuit

Implementing eFuse visual security of stored data using EDRAM

Dynamic noise mitigation in integrated circuit devices using local clock buffers

System for testing charge trap memory cells

System for testing charge trap memory cells

Implementing eFuse visual security of stored data using EDRAM

Method of optimizing wire RC for device performance and reliability

Multiple FET non-volatile memory with default logical state

FinFET power supply decoupling

Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage

Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage

Power gating and clock gating in wiring levels

Implementing eFuse visual security of stored data using EDRAM

High-density integrated circuit via capacitor

High-density integrated circuit via capacitor

Decoupling capacitor using finFET topology

Detection of initial state by eFuse array

Bias-temperature induced damage mitigation circuit

Bias-temperature induced damage mitigation circuit

Implementing hidden security key in eFuses

Implementing hidden security key in eFuses

Sensing of non-volatile memory cell having two complementary memory transistors

Sensing circuit for a non-volatile memory cell having two complementary memory transistors

Structure for metal oxide semiconductor capacitor

PRECISION INTRALEVEL METAL CAPACITOR FABRICATION

PRECISION INTRALEVEL METAL CAPACITOR FABRICATION

Structure for metal oxide semiconductor capacitor

Side gate assist in metal gate first process

IMPLEMENTING BURIED FET BELOW AND BESIDE FINFET ON BULK SUBSTRATE

Semiconductor chip with power gating through silicon vias

Implementing buried FET below and beside FinFET on bulk substrate

Method of implementing buried FET below and beside FinFET on bulk substrate

Implementing buried FET utilizing drain of finFET as gate of buried FET

Signal transmission reducing coupling caused delay variation

Interdigitated finFETs

Method of making semiconductor device with distinct multiple-patterned conductive tracks on a same level

Semiconductor device with distinct multiple-patterned conductive tracks on a same level

Precision IC resistor fabrication

Capacitor backup for SRAM

Capacitor backup for SRAM

Multiple-patterned semiconductor device channels

Semiconductor device channels

Semiconductor device channels

Multiple-patterned semiconductor device channels

Semiconductor device channels

Semiconductor device channels

Semiconductor chip with power gating through silicon vias

Method for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications

Signal path and method of manufacturing a multiple-patterned semiconductor device

Signal path of a multiple-patterned semiconductor device

Signal path of a multiple-patterned semiconductor device

Signal path and method of manufacturing a multiple-patterned semiconductor device

GATELESS FINFET

Signal path and method of manufacturing a multiple-patterned semiconductor device

Semiconductor chip with power gating through silicon vias

Implementing enhanced power supply distribution and decoupling utilizing TSV exclusion zone

Integrated decoupling capacitor utilizing through-silicon via

Integrated decoupling capacitor utilizing through-silicon via

FinFET with body contact

Implementing gate within a gate utilizing replacement metal gate process

IMPLEMENTING ISOLATED SILICON REGIONS IN SILICON-ON-INSULATOR (SOI) WAFERS USING BONDED-WAFER TECHNIQUE