Inventor profile of:

Van Hoa Lee

City:

Cedar Park, Texas

Country:

United States

Published Applications:

22

Last publication date:

2009-12-03

Top Assignees for applications by Van Hoa Lee

The entities that hold a legal rights for patent applications filed by inventor Lee Van Hoa:

Recent patent applications by Lee Van Hoa

Van Hoa Lee from Cedar Park, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2009-12-03
US20090300644A1
Physics

Detecting a deadlock condition by monitoring firmware inactivity during the system IPL process

#2 | 2009-01-20
US10142545
-

Method and apparatus for dynamically allocating and deallocating processors in a logical partitioned data processing system

#3 | 2008-08-07
US20080189509A1
Physics

Data processing system and computer program product to allow PCI host bridge (PHB) to handle pre-fetch read transactions on the PCI bus which access system memory through translation control entry (TCE) table

#4 | 2008-03-27
US20080077282A1
Physics

System and method to maintain data processing system operation in degraded system cooling condition

#5 | 2006-10-03
US10422681
-

Method and apparatus for recovery of partitions in a logical partitioned data processing system

#6 | 2006-06-20
US9798204
-

Nonvolatile logical partition system data management

#7 | 2006-02-16
US20060036789A1
Physics

Method to switch the lock-bits combination used to lock a page table entry upon receiving system reset exceptions

#8 | 2005-12-29
US20050289376A1
Physics

System and method to maintain data processing system operation in degraded system cooling condition

#9 | 2005-12-27
US10105125
-

Critical datapath error handling in a multiprocessor architecture

#10 | 2005-11-29
US9925584
-

Method, system, and product for booting a partition using one of multiple, different firmware images without rebooting other partitions

#11 | 2005-11-01
US9631723
-

Permanent open firmware PCI host bridge (PHB) unit addressing to support dynamic memory mapping and swapping of I/O drawers

#12 | 2005-10-06
US20050223185A1
Physics

Data processing system and computer program product for support of system memory addresses with holes

#13 | 2005-09-29
US20050216642A1
Physics

Method to allow PCI host bridge (PHB) to handle pre-fetch read transactions on the PCI bus which access system memory through translation control entry (TCE) table

#14 | 2005-09-06
US10142574
-

Method and apparatus for managing memory blocks in a logical partitioned data processing system

#15 | 2005-07-28
US20050166073A1
Physics

Method and apparatus to change the operating frequency of system core logic to maximize system memory bandwidth

#16 | 2005-06-28
US10339774
-

Method, system, and computer program product for creating and managing memory affinity in logically partitioned data processing systems

#17 | 2005-04-26
US10112477
-

Computer system serialization control method involving unlocking global lock of one partition, after completion of machine check analysis regardless of state of other partition locks

#18 | 2005-04-21
US20050086464A1
Physics

Technique for system initial program load or boot-up of electronic devices and systems

#19 | 2005-04-19
US9965000
-

Method and apparatus for verifying hardware implementation of a processor architecture in a logically partitioned data processing system

#20 | 2005-03-08
US9998047
-

Logical partition management apparatus and method for handling system reset interrupts

#21 | 2005-01-18
US10087920
-

Method and system to identify a memory corruption source within a multiprocessor system

#22 | 2005-01-11
US9833337
-

Method and apparatus to concurrently boot multiple processors in a non-uniform-memory-access machine

InventorID:

4069749 ⎘