Paul Caprioli

Processor with a register file that supports multiple-issue execution

Method and structure for pipelining of SIMD conditional moves

Circuitry and method for accessing an associative cache with parallel determination of data and data availability

Arithmetic early bypass

Using a transactional execution mechanism to free up processor resources used by a busy-waiting thread

Method for graphically displaying hardware performance simulators

Predicting a jump target based on a program counter and state information for a process

Deferring loads and stores when a load buffer or store buffer fills during execute-ahead mode

Method and apparatus for synchronizing threads on a processor that supports transactional memory

Method and apparatus for sampling instructions on a processor that supports speculative execution

Method and structure for coordinating instruction execution in out-of-order processor execution using an instruction including an artificial register dependency

Patchable and/or programmable pre-decode

Patchable and/or programmable decode using predecode selection

Technique for eliminating dead stores in a processor

Supporting out-of-order issue in an execute-ahead processor

Collapsible front-end translation for instruction fetch

Decoupling register bypassing from pipeline depth

Method and apparatus for selectively prefetching based on resource availability

Mechanism for hardware tracking of return address after tail call elimination of return-type instruction

Return address stack recovery in a speculative execution computing apparatus

Avoiding live-lock in a processor that supports speculative execution

Method and apparatus for suppressing duplicative prefetches for branch target cache lines

Method and apparatus for using multiple threads to spectulatively execute instructions

Generation of multiple checkpoints in a processor that supports speculative execution

Branch prediction accuracy in a processor that supports speculative execution

Cache replacement policy to mitigate pollution in multicore processors

Selectively performing fetches for store operations during speculative execution

Selective execution of deferred instructions in a processor that supports speculative execution

Mechanism for eliminating the restart penalty when reissuing deferred instructions

Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor

Avoiding register RAW hazards when returning from speculative execution

Method and structure for concurrent branch prediction in a processor

Branch target aware instruction prefetching technique

Entering scout-mode when stores encountered during execute-ahead mode exceed the capacity of the store buffer

Method and apparatus for avoiding read-after-write hazards in an execute-ahead processor

Method and apparatus for avoiding write-after-read hazards in an execute-ahead processor

Method and apparatus for avoiding write-after-write hazards in an execute-ahead processor

Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor to hide memory latency