Inventor profile of:

Erik E. Hagersten

City:

Uppsala

Country:

Sweden

Published Applications:

19

Last publication date:

2011-09-20

Top Assignees for applications by Erik E. Hagersten

The entities that hold a legal rights for patent applications filed by inventor Hagersten Erik E.:

Recent patent applications by Hagersten Erik E.

Erik E. Hagersten from Uppsala, SE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2011-09-20
US10821371
-

Multi-node system with global access states

#2 | 2011-08-30
US10821372
-

Multi-node computer system with proxy transaction to read data from a non-owning memory device

#3 | 2011-05-17
US10821412
-

Multi-node computer system employing a reporting mechanism for multi-node transactions

#4 | 2009-10-20
US10821394
-

Multi-node computer system implementing global access state dependent transactions

#5 | 2009-05-05
US10821564
-

Multi-node system with split ownership and access right coherence mechanism

#6 | 2009-05-05
US10422454
-

Multiprocessing systems employing hierarchical spin locks

#7 | 2008-04-22
US10817689
-

Performing virtual to global address translation in processing subsystem

#8 | 2008-04-15
US10817630
-

Multi-node system in which global address generated by processing subsystem includes global to local translation information

#9 | 2008-01-10
US20080010417A1
Physics

Read/Write Permission Bit Support for Efficient Hardware to Software Handover

#10 | 2007-11-08
US20070260821A1
Physics

DRAM remote access cache in local memory in a distributed shared memory system

#11 | 2007-11-01
US20070255908A1
Physics

Speculative directory lookup for sharing classification

#12 | 2007-11-01
US20070255907A1
Physics

Value-based memory coherence support

#13 | 2007-06-26
US10766698
-

Computer system employing bundled prefetching and null-data packet transmission

#14 | 2007-01-16
US10408691
-

Multiprocessing computer system employing capacity prefetching

#15 | 2006-10-10
US10610520
-

Computer system including a promise array

#16 | 2006-07-18
US10320758
-

System and method for reducing shared memory write overhead in multiprocessor systems

#17 | 2005-02-24
US20050044174A1
Physics

Multi-node computer system where active devices selectively initiate certain transactions using remote-type address packets

#18 | 2005-01-06
US20050005075A1
Physics

Multi-node computer system employing multiple memory response states

#19 | 2005-01-06
US20050005074A1
Physics

Multi-node system in which home memory subsystem stores global to local address translation information for replicating nodes

InventorID:

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