Haining S. Yang

HETEROJUNCTION TUNNELING FIELD EFFECT TRANSISTORS, AND METHODS FOR FABRICATING THE SAME

Hybrid interconnect structure for performance improvement and reliability enhancement

Hybrid interconnect structure for performance improvement and reliability enhancement

Hybrid interconnect structure for performance improvement and reliability enhancement

Structure and method of forming a transistor with asymmetric channel and source/drain regions

Structure and method to form E-fuse with enhanced current crowding

Heterojunction tunneling field effect transistors, and methods for fabricating the same

Replacement gate CMOS

Semiconductor devices having tensile and/or compressive stress and methods of manufacturing

Semiconductor devices having tensile and/or compressive stress and methods of manufacturing

Semiconductor transistors having reduced distances between gate electrode regions

Boost cell supply write assist

Hybrid interconnect structure for performance improvement and reliability enhancement

Carrier mobility enhanced channel devices and method of manufacture

Double patterning process for integrated circuit device manufacturing

Programmable PN anti-fuse

Electrical fuses and resistors having sublithographic dimensions

CMOS diodes with dual gate conductors, and methods for forming the same

Methods and systems involving electrically programmable fuses

Replacement gate CMOS

Body contacts for FET in SOI SRAM array

Field effect device including recessed and aligned germanium containing channel

METHOD TO INCREASE STRAIN ENHANCEMENT WITH SPACERLESS FET AND DUAL LINER PROCESS

Method for reducing tip-to-tip spacing between lines

Structure and method of forming a transistor with asymmetric channel and source/drain regions

SOI substrates and SOI devices, and methods for forming the same

High aspect ratio electroplated metal feature and method

Semiconductor device structure having enhanced performance FET device

FIELD EFFECT DEVICE WITH GATE ELECTRODE EDGE ENHANCED GATE DIELECTRIC AND METHOD FOR FABRICATION

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING

Electrical fuse having sublithographic cavities thereupon

CMOS devices having reduced threshold voltage variations and methods of manufacture thereof

Structure and method to form e-fuse with enhanced current crowding

Structure and method to integrate dual silicide with dual stress liner to improve CMOS performance

Structure and method to form dual silicide e-fuse

Carrier mobility enhanced channel devices and method of manufacture

FINFET WITH A V-SHAPED CHANNEL

High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching

Metal gate compatible flash memory gate stack

Complementary field effect transistors having embedded silicon source and drain regions

Semiconductor devices having tensile and/or compressive stress and methods of manufacturing

Low contact resistance metal contact

Dual damascene metal interconnect structure having a self-aligned via

Method and structure for relieving transistor performance degradation due to shallow trench isolation induced stress

Multiwalled carbon nanotube memory device

SRAM device structure including same band gap transistors having gate stacks with high-K dielectrics and same work function

Dual oxide stress liner

High aspect ratio electroplated metal feature and method

High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same

Electrical fuse and method of making

Dual workfunction silicide diode

Integration scheme for multiple metal gate work function structures

FINFET MEMORY DEVICE WITH DUAL SEPARATE GATES AND METHOD OF OPERATION

Electrical fuse and method of making

Methods and systems involving electrically programmable fuses

ELECTROMIGRATION RESISTANT INTERCONNECT STRUCTURE

Electrical fuses and resistors having sublithographic dimensions

Semiconductor transistors having reduced distances between gate electrode regions

Hybrid orientation substrate and method for fabrication thereof

Electrical fuse having sublithographic cavities thereupon

FinFET with sublithographic fin width

Partially gated FINFET with gate dielectric on only one sidewall

Multiwalled carbon nanotube memory device

Electrical fuse having a cavity thereupon

FinFET SRAM with asymmetric gate and method of manufacture thereof

DUAL STRESS LINER EFUSE

Method of forming an SOI substrate contact

METHODS OF PATTERNING SELF-ASSEMBLY NANO-STRUCTURE AND FORMING POROUS DIELECTRIC

Semiconductor structure and method of manufacture

ELECTRICAL FUSE WITH SUBLITHOGRAPHIC DIMENSION

SOI MOSFET WITH A METAL SEMICONDUCTOR ALLOY GATE-TO-BODY BRIDGE

Self-aligned and extended inter-well isolation structure

EXTENDED DEPTH INTER-WELL ISOLATION STRUCTURE

Method and structure for forming strained Si for CMOS devices

DOPANT DIFFUSION BARRIER LAYER TO PREVENT OUT DIFFUSION

STRUCTURE AND METHOD TO OPTIMIZE STRAIN IN CMOSFETs

STRUCTURE AND METHOD OF MAKING A SEMICONDUCTOR INTEGRATED CIRCUIT TOLERANT OF MIS-ALIGNMENT OF A METAL CONTACT PATTERN

Metal silicide alloy local interconnect

Low contact resistance metal contact

Non-planar fuse structure including angular bend

CMOS gate conductor having cross-diffusion barrier

Overlapped stressed liners for improved contacts

Silicon on insulator (SOI) field effect transistors (FETs) with adjacent body contacts

CONTACT STRUCTURE HAVING DIELECTRIC SPACER AND METHOD

STRUCTURE HAVING DUAL SILICIDE REGION AND RELATED METHOD

Process for making FinFET device with body contact and buried oxide junction isolation

Method and structure for controlling stress in a transistor channel

Semiconductor device structure having enhanced performance FET device

SOI MOSFET DEVICE WITH ADJUSTABLE THRESHOLD VOLTAGE

Method for dual stress liner

Sub-lithographic interconnect patterning using self-assembling polymers

Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost

Two-sided semiconductor-on-insulator structures and methods of manufacturing the same

Sub-lithographic gate length transistor using self-assembling polymers

Hybrid interconnect structure for performance improvement and reliability enhancement

Structure and method to form improved isolation in a semiconductor device

SUB-LITHOGRAPHIC FACETING FOR MOSFET PERFORMANCE ENHANCEMENT

Reversible electric fuse and antifuse structures for semiconductor devices

Device patterned with sub-lithographic features with variable widths

STRUCTURE AND METHOD FOR MULTIPLE HEIGHT FINFET DEVICES