Igor Arsovski

COMMUNICATION SCHEDULING BASED ON CROSSTALK DATA

PROACTIVE THERMAL MANAGEMENT OF A DETERMINISTIC PROCESSOR TO IMPROVE LATENCY, THROUGHPUT, AND RELIABILITY

Power Management of a Power Regulator in a Processor During High Current Events

Preemptive Processor Power Supply Regulator Feedback Modulation to Mitigate Voltage Overshoot and Undershoot

Optical Communication for Memory Disaggregation in High Performance Computing

Multi-sense amplifier based access to a single port of a memory cell

Multiple sense amplifier and data path-based pseudo dual port SRAM

Customer-transparent logic redundancy for improved yield

Sensing circuits for charge trap transistors

Multi-port high performance memory

Multi-port memory architecture for a systolic array

Hermetic barrier for semiconductor device

Parallel-prefix adder and method

Memory built-in self test error correcting code (MBIST ECC) for low voltage memories

Activity-aware supply voltage and bias voltage compensation

High-density high-bandwidth static random access memory (SRAM) with phase shifted sequential read

Parallel-prefix adder and method

Ternary content addressable memory

Customer-transparent logic redundancy for improved yield

Sequential read mode static random access memory (SRAM)

Zero test time memory using background built-in self-test

Dynamic power analysis with per-memory instance activity customization

Ternary content addressable memory

Sense-line muxing scheme

Zero test time memory using background built-in self-test

Bending circuit for static random access memory (SRAM) self-timer

INTERPOSER HEATER FOR HIGH BANDWIDTH MEMORY APPLICATIONS

Ternary content addressable memory (TCAM) for multi bit miss detect circuit

Transmission system having duplicate transmission systems for individualized precharge and output timing

Customer-transparent logic redundancy for improved yield

Algorithmic N search/M write ternary content addressable memory (TCAM)

Self pre-charging memory circuits

Double bandwidth algorithmic memory array

Timing/power risk optimized selective voltage binning using non-linear voltage slope

Pre-test power-optimized bin reassignment following selective voltage binning

Application specific integrated circuit (ASIC) test screens and selection of such screens

Environmentally aware mobile computing devices

Content-addressable memory having multiple reference matchlines to reduce latency

Matchline precharge architecture for self-reference matchline sensing

Ternary content addressable memory

TCAM structures with reduced power supply noise

Composite views for IP blocks in ASIC designs

Pre-test power-optimized bin reassignment following selective voltage binning

Converting an XY TCAM to a value TCAM

Minimization of bias temperature instability (BTI) degradation in circuits

Scoped search engine

Customer-transparent logic redundancy for improved yield

Customer-transparent logic redundancy for improved yield

Bias temperature instability state detection and correction

High density search engine

Learning artificial neural network using ternary content addressable memory (TCAM)

Limiting skew between different device types to meet performance requirements of an integrated circuit

Stress balancing of circuits

Converting an XY TCAM to a value TCAM

Single ended sensing circuits for signal lines

Partial update in a ternary content addressable memory

Partial update in a ternary content addressable memory

Leakage reduction in output driver circuits

Self-timed, single-ended sense amplifier

STATISTICAL POWER ESTIMATION

Implementing computational memory from content-addressable memory

Determining overall optimal yield point for a semiconductor wafer

Methods and circuits for disrupting integrated circuit function

Two phase search content addressable memory with power-gated main-search

Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system

Content addressable memory early-predict late-correct single ended sensing

Majority dominant power scheme for repeated structures and structures thereof

Majority dominant power scheme for repeated structures and structures thereof

Vdiff max limiter in SRAMs for improved yield and power

Static random access memory (SRAM) write assist circuit with leakage suppression and level control

Word-line level shift circuit

Methods and systems for adjusting wordline up-level voltage to improve production yield relative to SRAM-cell stability

SRAM having wordline up-level voltage adjustable to assist bitcell stability and design structure for same

Method and device for measuring integrated circuit power supply noise and calibration of power supply noise analysis models

Content addressable memory with concurrent read and search/compare operations at the same memory cell

SRAM delay circuit that tracks bitcell characteristics

Method and apparatus for configuring a content-addressable memory (CAM) design as binary CAM or ternary CAM

Word-line level shift circuit

Method for low power sensing in a multi-port SRAM using pre-discharged bit lines

Low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines

Environmental and computing cost reduction with improved reliability in workload assignment to distributed computing nodes

Critical path redundant logic for mitigation of hardware across chip variation

Adaptive noise suppression using a noise look-up table

Circuit structure and method for digital integrated circuit performance screening

Apparatus and method for low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines

Apparatus and method for low power sensing in a multi-port SRAM using pre-discharged bit lines

Structure for implementing memory array device with built in computation capability

Apparatus and method for implementing memory array device with built in computational capability

STRUCTURE FOR IMPLEMENTING ENHANCED CONTENT ADDRESSABLE MEMORY PERFORMANCE CAPABILITY

Design structure for implementing matrix-based search capability in content addressable memory devices

Content addressable memory with concurrent two-dimensional search capability in both row and column directions

Apparatus and method for implementing matrix-based search capability in content addressable memory devices

Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path

Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design

SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION

Device Threshold Calibration Through State Dependent Burnin

Design structures of powering on integrated circuit

Method and systems of powering on integrated circuit

Design structures, method and systems of powering on integrated circuit

E-FUSE AND METHOD