Poughkeepsie, New York
United States
9
2008-11-13
The entities that hold a legal rights for patent applications filed by inventor Burrell Lloyd G.:
Lloyd G. Burrell from Poughkeepsie, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Methods for forming co-planar wafer-scale chip packages
#2 | 2008-03-27METHOD OF FABRICATING A WIRE BOND PAD WITH Ni/Au METALLIZATION
#3 | 2006-08-24Wirebond crack sensor for low-k die
#4 | 2006-08-08Copper to aluminum interlayer interconnect using stud and via liner
#5 | 2006-05-25Methods for forming co-planar wafer-scale chip packages
#6 | 2006-05-02Copper to aluminum interlayer interconnect using stud and via liner
#7 | 2005-06-21Support structures for wirebond regions of contact pads over low modulus materials
#8 | 2005-04-07Method of fabricating a wire bond pad with Ni/Au metallization
#9 | 2005-03-31Semiconductor device having a composite layer in addition to a barrier layer between copper wiring and aluminum bond pad
4145069 ⎘