Kaoshing
Taiwan
27
2012-02-16
The entities that hold a legal rights for patent applications filed by inventor Ho ChiaHua:
ChiaHua Ho from Kaoshing, TW has applied for patents for these inventions. The list has both pending applications and granted patents:
Resistance random access memory structure for enhanced retention
#2 | 2010-08-26Method of a multi-level cell resistance random access memory with metal oxides
#3 | 2010-08-05Resistor random access memory cell device
#4 | 2009-12-10Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states
#5 | 2009-09-24Memory device manufacturing method
#6 | 2009-04-23Method for manufacturing a resistor random access memory with a self-aligned air gap insulator
#7 | 2009-02-05Resistor random access memory structure having a defined small area of electrical contact
#8 | 2008-12-11Resistance memory with tungsten compound and manufacturing
#9 | 2008-11-20Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states
#10 | 2008-07-24Multilevel-cell memory structures employing multi-memory with tungsten oxides and manufacturing method
#11 | 2008-07-03Resistor random access memory cell device
#12 | 2008-06-12Multi-level cell resistance random access memory with metal oxides
#13 | 2008-05-22Resistance random access memory structure for enhanced retention
#14 | 2008-04-24Method for Manufacturing a Resistor Random Access Memory with a Self-Aligned Air Gap insulator
#15 | 2008-04-24Method for manufacturing a resistor random access memory with reduced active area and reduced contact areas
#16 | 2008-04-24Bistable Resistance Random Access Memory Structures with Multiple Memory Layers and Multilevel Memory States
#17 | 2008-04-24Methods of operating a bistable resistance random access memory with multiple memory layers and multilevel memory states
#18 | 2008-04-24Method and apparatus for non-volatile multi-bit memory
#19 | 2007-12-06Resistor random access memory cell with reduced active area and reduced contact areas
#20 | 2007-10-18Memory device and manufacturing method
#21 | 2007-07-12Method for forming self-aligned thermal isolation cell for a variable resistance memory array
#22 | 2007-07-12Method for Fabricating a Pillar-Shaped Phase Change Memory Element
#23 | 2007-07-05Chalcogenide layer etching method
#24 | 2007-05-24Memory cell device and manufacturing method
#25 | 2006-12-21Method for manufacturing a narrow structure on an integrated circuit
#26 | 2006-03-28Bistable magnetic device using soft magnetic intermediary material
#27 | 2005-09-08MRAM array employing spin-filtering element connected by spin-hold element to MRAM cell structure for enhanced magnetoresistance
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