Inventor profile of:

Robert J. Devins

City:

Essex Junction, Vermont

Country:

United States

Published Applications:

16

Last publication date:

2008-12-18

Top Assignees for applications by Robert J. Devins

The entities that hold a legal rights for patent applications filed by inventor Devins Robert J.:

Recent patent applications by Devins Robert J.

Robert J. Devins from Essex Junction, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2008-12-18
US20080312896A1
Physics

Optimal bus operation performance in a logic simulation environment

#2 | 2008-09-11
US20080222583A1
Physics

Method and system for logic verification using mirror interface

#3 | 2008-07-31
US20080184193A1
Physics

System and method for developing embedded software in-situ

#4 | 2008-06-05
US20080133206A1
Physics

Method of switching external models in an automated system-on-chip integrated circuit design verification system

#5 | 2008-04-01
US9683677
-

Method of switching external models in an automated system-on-chip integrated circuit design verification system

#6 | 2007-08-30
US20070204246A1
Physics

METHOD AND SYSTEM FOR LOGIC VERIFICATION USING MIRROR INTERFACE

#7 | 2007-07-19
US20070168733A1
Physics

Method and system of coherent design verification of inter-cluster interactions

#8 | 2007-06-14
US20070136559A1
Physics

Method and system of communicating between peer processors in SoC environment

#9 | 2007-02-13
US10665289
-

Method and system for graphics rendering using hardware-event-triggered execution of captured graphics hardware instructions

#10 | 2006-10-12
US20060229858A1
Physics

Optimal bus operation performance in a logic simulation environment

#11 | 2006-03-23
US20060064296A1
Physics

Method and system of design verification

#12 | 2006-03-02
US20060047939A1
Physics

METHOD AND APPARATUS FOR INITIALIZING MULTIPLE PROCESSORS RESIDING IN AN INTEGRATED CIRCUIT

#13 | 2005-10-04
US9283386
-

Method and system for graphics rendering using captured graphics hardware instructions

#14 | 2005-06-30
US20050144577A1
Physics

Method and system for logic verification using mirror interface

#15 | 2005-03-15
US9495236
-

Method for re-using system-on-chip verification software in an operating system

#16 | 2005-03-08
US9826035
-

Method and system for logic verification using mirror interface

InventorID:

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