Boeblingen
Germany
42
2018-10-04
The entities that hold a legal rights for patent applications filed by inventor Barowski Harry:
Harry Barowski from Boeblingen, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
Cross bar switch structure for highly congested environments
#2 | 2018-07-26Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature
#3 | 2018-07-05Area sharing between multiple large block synthesis (LBS) blocks
#4 | 2018-06-21Testing content addressable memory and random access memory
#5 | 2018-05-31Testing content addressable memory and random access memory
#6 | 2018-05-31Placement clustering-based white space reservation
#7 | 2018-04-26Testing content addressable memory and random access memory
#8 | 2018-04-12Layout of large block synthesis blocks in integrated circuits
#9 | 2018-04-12Layout of large block synthesis blocks in integrated circuits
#10 | 2017-12-07Area sharing between multiple large block synthesis (LBS) blocks
#11 | 2017-07-27Layout of large block synthesis blocks in integrated circuits
#12 | 2017-07-27Layout of large block synthesis blocks in integrated circuits
#13 | 2017-01-05De-coupling capacitance placement
#14 | 2017-01-05De-coupling capacitance placement
#15 | 2016-09-06Write address synchronization in 2 read/1write SRAM arrays
#16 | 2016-08-02Write address synchronization in 2 read/1write SRAM arrays
#17 | 2016-06-23Pipelining out-of-order instructions
#18 | 2016-03-10Through-silicon via access device for integrated circuits
#19 | 2016-03-10Through-silicon via access device for integrated circuits
#20 | 2016-03-10Integrated circuit design changes using through-silicon vias
#21 | 2015-08-06Transferring heat through an optical layer of integrated circuitry
#22 | 2015-02-05Techniques for increasing instruction issue rate and reducing latency in an out-of order processor
#23 | 2014-04-03Transferring heat through an optical layer of integrated circuitry
#24 | 2014-03-20Charge recycling between power domains of integrated circuits
#25 | 2013-12-26Pipelining out-of-order instructions
#26 | 2013-08-29Three-dimensional permute unit for a single-instruction multiple-data processor
#27 | 2013-05-30Charge recycling between power domains of integrated circuits
#28 | 2012-11-29Power down of execution units for issued instruction accumulation when issue rate of instructions falls below threshold and at least two are independent
#29 | 2012-11-15Optimized semiconductor packaging in a three-dimensional stack
#30 | 2012-07-26Transferring heat through an optical layer of integrated circuitry
#31 | 2012-06-14Multistage, hybrid synthesis processing facilitating integrated circuit layout
#32 | 2012-06-14Integrated circuit package connected to a data transmission medium
#33 | 2012-06-14Integrated circuit package connected to an optical data transmission medium using a coolant
#34 | 2012-05-03Heat sink integrated power delivery and distribution for integrated circuits
#35 | 2012-05-03Thermal power plane for integrated circuits
#36 | 2012-05-03Optimized semiconductor packaging in a three-dimensional stack
#37 | 2010-09-09Power gating processor execution units when number of instructions issued per cycle falls below threshold and are independent until instruction queue is full
#38 | 2009-10-01MULTI-CYCLE REGISTER FILE BYPASS
#39 | 2009-03-10Method and system for data dependent performance increment and power reduction
#40 | 2008-11-20Formally deriving a minimal clock-gating scheme
#41 | 2007-07-19Method to Reduce Leakage Within a Sequential Network and Latch Circuit
#42 | 2007-07-19Circuit Arrangement and Method to Reduce Leakage Power and to Increase the Performance of a Circuit
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