Inventor profile of:

Stephan NIEL

City:

Greasque

Country:

France

Published Applications:

19

Last publication date:

2017-03-23

Top Assignees for applications by Stephan NIEL

The entities that hold a legal rights for patent applications filed by inventor NIEL Stephan:

Recent patent applications by NIEL Stephan

Stephan NIEL from Greasque, FR has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2017-03-23
US20170084749A1
Electricity

Vertical memory cell with non-self-aligned floating drain-source implant

#2 | 2017-01-12
US20170011804A1
Physics

Dual non-volatile memory cell comprising an erase transistor

#3 | 2016-11-17
US20160336070A1
Physics

Twin memory cell interconnection structure

#4 | 2016-06-23
US20160181265A1
Electricity

Memory cell having a vertical selection gate formed in an FDSOI substrate

#5 | 2016-03-10
US20160071598A1
Physics

Method for biasing an embedded source plane of a non-volatile memory having vertical select gates

#6 | 2015-12-03
US20150348981A1
Electricity

Individually read-accessible twin memory cells

#7 | 2015-12-03
US20150348640A1
Physics

Dual non-volatile memory cell comprising an erase transistor

#8 | 2015-12-03
US20150348635A1
Physics

Method for programming a non-volatile memory cell comprising a shared select transistor gate

#9 | 2015-11-12
US20150325581A1
Electricity

Integrated circuit protected from short circuits caused by silicide

#10 | 2015-08-20
US20150236031A1
Electricity

Vertical memory cell with non-self-aligned floating drain-source implant

#11 | 2015-04-30
US20150117117A1
Electricity

Memory cell comprising non-self-aligned horizontal and vertical control gates

#12 | 2015-04-30
US20150117109A1
Physics

Hot-carrier injection programmable memory and method of programming such a memory

#13 | 2014-09-04
US20140246720A1
Electricity

INTEGRATED CIRCUIT PROTECTED FROM SHORT CIRCUITS CAUSED BY SILICIDE

#14 | 2014-07-10
US20140191291A1
Electricity

Method of manufacturing a non-volatile memory

#15 | 2014-04-10
US20140097481A1
Electricity

Non-volatile memory with vertical selection transistors

#16 | 2013-09-05
US20130229875A1
Physics

Method of reading and writing nonvolatile memory cells

#17 | 2013-09-05
US20130228846A1
Electricity

Nonvolatile memory cells with a vertical selection gate of variable depth

#18 | 2010-02-25
US20100044874A1
Electricity

Integrated circuit of decreased size

#19 | 2009-07-23
US20090186460A1
Electricity

Method for manufacturing an EEPROM cell

InventorID:

421726 ⎘