Inventor profile of:

Jody Bern Joyner

City:

Austin, Texas

Country:

United States

Published Applications:

18

Last publication date:

2009-04-28

Top Assignees for applications by Jody Bern Joyner

The entities that hold a legal rights for patent applications filed by inventor Joyner Jody Bern:

Recent patent applications by Joyner Jody Bern

Jody Bern Joyner from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2009-04-28
US10425421
-

Data processing system with backplane and processor books configurable to support both technical and commercial workloads

#2 | 2009-03-10
US10313277
-

High speed memory cloning facility via a lockless multiprocessor mechanism

#3 | 2008-08-28
US20080209163A1
Physics

DATA PROCESSING SYSTEM WITH BACKPLANE AND PROCESSOR BOOKS CONFIGURABLE TO SUPPPRT BOTH TECHNICAL AND COMMERCIAL WORKLOADS

#4 | 2006-06-27
US10313293
-

Dynamic data routing mechanism for a high speed memory cloner

#5 | 2006-02-07
US10313296
-

High speed memory cloning facility via a source/destination switching mechanism

#6 | 2006-01-10
US10313323
-

High speed memory cloner within a data processing system

#7 | 2006-01-10
US10313322
-

Imprecise cache line protection mechanism during a memory clone operation

#8 | 2005-09-01
US20050193174A1
Physics

System bus read data transfers with data ordering control bits

#9 | 2005-08-09
US10313328
-

Data processing system with naked cache line write operations

#10 | 2005-07-07
US20050149692A1
Physics

Multiprocessor data processing system having scalable data interconnect and data routing mechanism

#11 | 2005-07-07
US20050149660A1
Physics

Multiprocessor data processing system having a data routing mechanism regulated through control communication

#12 | 2005-07-05
US10313281
-

High speed memory cloning facility via a coherently done mechanism

#13 | 2005-06-21
US9918812
-

Method and apparatus for transmitting packets within a symmetric multiprocessor system

#14 | 2005-05-24
US10313295
-

Dynamic software accessibility to a microprocessor system with a high speed memory cloner

#15 | 2005-05-10
US10313288
-

High speed memory cloner with extended cache coherency protocols and responses

#16 | 2005-03-29
US9436421
-

System bus read data transfers with data ordering control bits

#17 | 2005-03-08
US9915668
-

Robust system bus recovery

#18 | 2005-01-25
US9436901
-

Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response

InventorID:

4243077 ⎘