Inventor profile of:

Mark van Dal

City:

Heverlee

Country:

Belgium

Published Applications:

30

Last publication date:

2020-04-09

Top Assignees for applications by Mark van Dal

The entities that hold a legal rights for patent applications filed by inventor Dal Mark van:

Recent patent applications by Dal Mark van

Mark van Dal from Heverlee, BE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2020-04-09
US20200111894A1
Electricity

Semiconductor device and formation thereof

#2 | 2017-10-26
US20170309725A1
Electricity

Semiconductor device and formation thereof

#3 | 2017-01-05
US20170005045A1
Electricity

Semiconductor device and method including an intertial mass element

#4 | 2016-02-25
US20160056270A1
Electricity

Structure and method for defect passivation to reduce junction leakage for finfet device

#5 | 2016-02-18
US20160049477A1
Electricity

III-V compound semiconductor device having dopant layer and method of making the same

#6 | 2015-10-15
US20150295064A1
Electricity

Semiconductor device and formation thereof

#7 | 2015-10-01
US20150279964A1
Electricity

Semiconductor device and formation thereof

#8 | 2015-06-18
US20150171206A1
Electricity

Epitaxially Growing III-V Contact Plugs for MOSFETs

#9 | 2014-09-18
US20140273383A1
Electricity

MOSFETs with channels on nothing and methods for forming the same

#10 | 2014-09-18
US20140264608A1
Electricity

Ditches near semiconductor fins and methods for forming the same

#11 | 2014-09-18
US20140264592A1
Electricity

Barrier layer for FinFET channels

#12 | 2014-09-11
US20140252478A1
Electricity

FinFET with channel backside passivation layer device and method

#13 | 2014-08-28
US20140239347A1
Electricity

Structure and method for defect passivation to reduce junction leakage for finFET device

#14 | 2014-06-12
US20140159165A1
Electricity

Faceted finFET

#15 | 2014-05-22
US20140138770A1
Electricity

Device with a strained Fin

#16 | 2014-03-06
US20140061801A1
Electricity

Fin field effect transistor layout for stress optimization

#17 | 2013-11-14
US20130299895A1
Electricity

III-V COMPOUND SEMICONDUCTOR DEVICE HAVING DOPANT LAYER AND METHOD OF MAKING THE SAME

#18 | 2013-10-03
US20130256784A1
Electricity

MOSFETs with channels on nothing and methods for forming the same

#19 | 2013-10-03
US20130256759A1
Electricity

FinFET with a buried semiconductor material between two fins

#20 | 2013-09-12
US20130234205A1
Electricity

Nickelide source/drain structures for CMOS transistors

#21 | 2012-12-20
US20120319211A1
Electricity

Strained channel field effect transistor

#22 | 2012-12-20
US20120319167A1
Electricity

Mask-less and implant free formation of complementary tunnel field effect transistors

#23 | 2012-04-12
US20120088344A1
Electricity

Method of fabricating a semiconductor device having an epitaxy region

#24 | 2011-11-22
US12900895
-

Method of fabricating a semiconductor device having an epitaxy region

#25 | 2010-02-25
US20100044760A1
Electricity

SELF-ALIGNED IMPACT-IONIZATION FIELD EFFECT TRANSISTOR

#26 | 2010-02-04
US20100028809A1
Physics

Double patterning for lithography to increase feature spatial density

#27 | 2009-12-10
US20090302389A1
Electricity

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH DIFFERENT METALLIC GATES

#28 | 2009-10-01
US20090242987A1
Electricity

Double-gate semiconductor devices having gates with different work functions and methods of manufacture thereof

#29 | 2008-10-23
US20080258186A1
Electricity

Source and Drain Formation in Silicon on Insulator Device

#30 | 2008-10-02
US20080237871A1
Electricity

Method of Manufacturing a Semiconductor Device and Semiconductor Device Obtained With Such a Method

InventorID:

429851 ⎘